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 ST72321Bxxx-Auto
8-bit MCU for automotive with 32 to 60 Kbyte Flash/ROM, ADC, 5 timers, SPI, SCI, I2C interface
Features
Memories
32 to 60 Kbyte dual voltage High Density Flash (HDFlash) ROM with readout protection capability. In-application programming and incircuit programming for HDFlash devices 1 to 2 Kbyte RAM HDFlash endurance: 100 cycles, data retention 20 years
LQFP64 10 x 10
LQFP64 14 x 14
LQFP44 10 x 10
Up to 48 I/O ports
Clock, reset and supply management
48/32/24 multifunctional bidirectional I/O lines 34/22/17 alternate function lines 16/12/10 high sink outputs
Enhanced low voltage supervisor (LVD) for main supply and auxiliary voltage detector (AVD) with interrupt capability Clock sources: crystal/ceramic resonator oscillators, internal RC oscillator and bypass for external clock PLL for 2x frequency multiplication 4 power saving modes: Halt, Active Halt, Wait and Slow
5 timers
Interrupt management
Nested interrupt controller 14 interrupt vectors plus TRAP and RESET Top Level Interrupt (TLI) pin on 64-pin devices 15/9 external interrupt lines (on 4 vectors)
Main clock controller with Real-time base, Beep and Clock-out capabilities Configurable watchdog timer Two 16-bit timers with 2 input captures, 2 output compares, external clock input on 1 timer, PWM and pulse generator modes 8-bit PWM auto-reload timer with 2 input captures, 4 PWM outputs, output compare and time base interrupt, external clock with event detector
3 communications interfaces
1 analog peripheral (low current coupling)
SPI synchronous serial interface SCI asynchronous serial interface 2 I C multimaster interface
10-bit ADC with up to 16 input ports
Development tools
Full HW/SW development pkg, ICT capability
Table 1.
Device summary
Prog. memory Flash/ROM 60 Kbytes Flash/ROM 48 Kbytes Flash/ROM 32 Kbytes RAM (stack) 2048 (256) bytes 1536 (256) bytes 1024 (256) bytes 3.8 to 5.5V Up to -40 to 125C Oper. voltage Temp. range Package LQFP64 LQFP44 LQFP64 LQFP44 LQFP64 LQFP44 14x14 10x10 10x10 14x14 10x10 10x10 14x14 10x10 10x10
Device ST72321BR9-Auto ST72321BAR9-AUTO ST72321BJ9-Auto ST72321BR7-Auto ST72321BAR7-Auto ST72321BJ7-Auto ST72321BR6-Auto ST72321BAR6-Auto ST72321BJ6-Auto
October 2007
Rev 1
1/247
www.st.com 1
Contents
ST72321Bxxx-Auto
Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
1.1 1.2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Differences between ST72321B-Auto and ST72321B datasheets . . . . . . 20
1.2.1 1.2.2 1.2.3 Principal differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Minor content differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Editing and formatting differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2
Package pinout and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
2.1 2.2 Package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3 4
Register and memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Flash program memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
4.3.1 Readout protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
ICC interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 ICP (in-circuit programming) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 IAP (in-application programming) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Related documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Flash control/status register (FCSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
5
Central processing unit (CPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
5.1 5.2 5.3 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 CPU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
5.3.1 5.3.2 5.3.3 5.3.4 5.3.5 Accumulator (A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Index registers (X and Y) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Program counter (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Condition code (CC) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Stack pointer (SP) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
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Contents
6
Supply, reset and clock management . . . . . . . . . . . . . . . . . . . . . . . . . . 44
6.1 6.2 6.3 6.4 6.5 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Phase locked loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Multi-oscillator (MO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Reset sequence manager (RSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
6.5.1 6.5.2 6.5.3 6.5.4 6.5.5 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Asynchronous external RESET pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 External power-on RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Internal low voltage detector (LVD) RESET . . . . . . . . . . . . . . . . . . . . . . 48 Internal watchdog RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
6.6
System integrity management (SI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
6.6.1 6.6.2 6.6.3 6.6.4 6.6.5 Low voltage detector (LVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Auxiliary voltage detector (AVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 System Integrity (SI) Control/Status register (SICSR) . . . . . . . . . . . . . . 53
7
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
7.1 7.2 7.3 7.4 7.5 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Masking and processing flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Interrupts and low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Concurrent and nested management . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Interrupt register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
7.5.1 7.5.2 CPU CC register interrupt bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Interrupt software priority registers (ISPRx) . . . . . . . . . . . . . . . . . . . . . . 60
7.6
External interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
7.6.1 7.6.2 I/O port interrupt sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 External interrupt control register (EICR) . . . . . . . . . . . . . . . . . . . . . . . . 64
8
Power saving modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
8.1 8.2 8.3 8.4 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Slow mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Active Halt and Halt modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
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Contents 8.4.1 8.4.2
ST72321Bxxx-Auto Active Halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
9
I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
9.1 9.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
9.2.1 9.2.2 9.2.3 Input modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Output modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
9.3 9.4 9.5
I/O port implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
10
Watchdog timer (WDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
10.1 10.2 10.3 10.4 10.5 10.6 10.7 10.8 10.9 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 How to program the watchdog timeout . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Hardware watchdog option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Using Halt mode with the WDG (WDGHALT option) . . . . . . . . . . . . . . . . 85 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
10.9.1 Control register (WDGCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
11
Main clock controller with real-time clock and beeper (MCC/RTC) . . 87
11.1 11.2 11.3 11.4 11.5 11.6 11.7 11.8 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Programmable CPU clock prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Clock-out capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Real-time clock timer (RTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Beeper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Main clock controller registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
11.8.1 MCC control/status register (MCCSR) . . . . . . . . . . . . . . . . . . . . . . . . . . 89
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ST72321Bxxx-Auto 11.8.2
Contents MCC beep control register (MCCBCR) . . . . . . . . . . . . . . . . . . . . . . . . . 90
12
PWM auto-reload timer (ART) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
12.1 12.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
12.2.1 12.2.2 12.2.3 12.2.4 12.2.5 12.2.6 12.2.7 12.2.8 12.2.9 Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Counter clock and prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Counter and prescaler initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Output compare control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Independent PWM signal generation . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Output compare and time base interrupt . . . . . . . . . . . . . . . . . . . . . . . . 95 External clock and event detector mode . . . . . . . . . . . . . . . . . . . . . . . . 95 Input capture function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 External interrupt capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
12.3
ART registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
12.3.1 12.3.2 12.3.3 12.3.4 12.3.5 12.3.6 12.3.7 Control/status register (ARTCSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Counter access register (ARTCAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Auto-reload register (ARTARR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 PWM control register (PWMCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Duty cycle registers (PWMDCRx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Input capture control / status register (ARTICCSR) . . . . . . . . . . . . . . . 101 Input capture registers (ARTICRx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
13
16-bit timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
13.1 13.2 13.3 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
13.3.1 13.3.2 13.3.3 13.3.4 13.3.5 13.3.6 13.3.7 Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 External clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 Input capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Output compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Forced compare output capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 One Pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 Pulse width modulation mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
13.4 13.5
Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
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13.6 13.7
Summary of timer modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 16-bit timer registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
13.7.1 13.7.2 13.7.3 13.7.4 13.7.5 13.7.6 13.7.7 13.7.8 13.7.9 Control register 1 (CR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 Control register 2 (CR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 Control/status register (CSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 Input capture 1 high register (IC1HR) . . . . . . . . . . . . . . . . . . . . . . . . . 121 Input capture 1 low register (IC1LR) . . . . . . . . . . . . . . . . . . . . . . . . . . 122 Output compare 1 high register (OC1HR) . . . . . . . . . . . . . . . . . . . . . . 122 Output compare 1 low register (OC1LR) . . . . . . . . . . . . . . . . . . . . . . . 122 Output compare 2 high register (OC2HR) . . . . . . . . . . . . . . . . . . . . . . 122 Output compare 2 low register (OC2LR) . . . . . . . . . . . . . . . . . . . . . . . 123
13.7.10 Counter high register (CHR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 13.7.11 Counter low register (CLR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 13.7.12 Alternate counter high register (ACHR) . . . . . . . . . . . . . . . . . . . . . . . . 123 13.7.13 Alternate counter low register (ACLR) . . . . . . . . . . . . . . . . . . . . . . . . . 124 13.7.14 Input capture 2 high register (IC2HR) . . . . . . . . . . . . . . . . . . . . . . . . . 124 13.7.15 Input capture 2 low register (IC2LR) . . . . . . . . . . . . . . . . . . . . . . . . . . 124
14
Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
14.1 14.2 14.3 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
14.3.1 14.3.2 14.3.3 14.3.4 14.3.5 14.3.6 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 Slave select management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 Master mode operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 Master mode transmit sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 Slave mode operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 Slave mode transmit sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
14.4 14.5
Clock phase and clock polarity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 Error flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
14.5.1 14.5.2 14.5.3 14.5.4 Master mode fault (MODF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 Overrun condition (OVR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 Write collision error (WCOL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 Single master systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
14.6
Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
14.6.1 Using the SPI to wake up the MCU from Halt mode . . . . . . . . . . . . . . 135
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14.7 14.8
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 SPI registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
14.8.1 14.8.2 14.8.3 Control register (SPICR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 Control/status register (SPICSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 Data I/O register (SPIDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
15
Serial communications interface (SCI) . . . . . . . . . . . . . . . . . . . . . . . . 140
15.1 15.2 15.3 15.4 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
15.4.1 15.4.2 15.4.3 Serial data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
15.5 15.6 15.7
Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 SCI registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
15.7.1 15.7.2 15.7.3 15.7.4 15.7.5 15.7.6 15.7.7 Status register (SCISR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 Control register 1 (SCICR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 Control register 2 (SCICR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 Data register (SCIDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 Baud rate register (SCIBRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 Extended receive prescaler division register (SCIERPR) . . . . . . . . . . 157 Extended transmit prescaler division register (SCIETPR) . . . . . . . . . . 158
16
I2C bus interface (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
16.1 16.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
16.2.1 16.2.2 I2C master features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 I2C slave features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
16.3
General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
16.3.1 16.3.2 16.3.3 Mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 Communication flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 SDA/SCL line control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
16.4
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
16.4.1 Slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
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ST72321Bxxx-Auto Master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
16.5 16.6 16.7
Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
16.7.1 16.7.2 16.7.3 16.7.4 16.7.5 16.7.6 16.7.7 I2C control register (CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 I2C status register 1 (SR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 I2C status register 2 (SR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 I2C clock control register (CCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 I2C data register (DR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 I2C own address register (OAR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 I2C own address register (OAR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
17
10-bit A/D converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
17.1 17.2 17.3 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
17.3.1 17.3.2 17.3.3 A/D converter configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 Starting the conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 Changing the conversion channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
17.4 17.5 17.6
Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 ADC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
17.6.1 17.6.2 17.6.3 17.6.4 Control/status register (ADCCSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 Data register (ADCDRH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 Data register (ADCDRL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 ADC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
18
Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
18.1 CPU addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
18.1.1 18.1.2 18.1.3 18.1.4 18.1.5 18.1.6 18.1.7 Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 Immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 Indexed (no offset, short, long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 Indirect (short, long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 Indirect Indexed (Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 Relative (Direct, Indirect) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
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18.2
Instruction groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
18.2.1 Using a prebyte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
19
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
19.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
19.1.1 19.1.2 19.1.3 19.1.4 19.1.5 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
19.2
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
19.2.1 19.2.2 19.2.3 Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
19.3
Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
19.3.1 19.3.2 19.3.3 19.3.4 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 Operating conditions with low voltage detector (LVD) . . . . . . . . . . . . . 194 Auxiliary voltage detector (AVD) thresholds . . . . . . . . . . . . . . . . . . . . . 194 External voltage detector (EVD) thresholds . . . . . . . . . . . . . . . . . . . . . 195
19.4
Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
19.4.1 19.4.2 19.4.3 Current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 Supply and clock managers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 On-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
19.5
Clock and timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
19.5.1 19.5.2 19.5.3 19.5.4 19.5.5 General timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 External clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 Crystal and ceramic resonator oscillators . . . . . . . . . . . . . . . . . . . . . . 200 RC oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
19.6
Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
19.6.1 19.6.2 RAM and hardware registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
19.7
EMC (electromagnetic compatibility) characteristics . . . . . . . . . . . . . . . 204
19.7.1 19.7.2 19.7.3 Functional EMS (electromagnetic susceptibility) . . . . . . . . . . . . . . . . . 204 EMI (electromagnetic interference) . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . 206
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19.8
I/O port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
19.8.1 19.8.2 General characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 Output driving current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
19.9
Control pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
19.9.1 19.9.2 Asynchronous RESET pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 ICCSEL/VPP pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
19.10 Timer peripheral characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 19.11 Communication interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . 215
19.11.1 SPI (serial peripheral interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 19.11.2 I2C - inter IC control interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
19.12 10-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
19.12.1 Analog power supply and reference pins . . . . . . . . . . . . . . . . . . . . . . . 221 19.12.2 General PCB design guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 19.12.3 ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
20
Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
20.1 20.2 20.3 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 Soldering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
20.3.1 Compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
21
Device configuration and ordering information . . . . . . . . . . . . . . . . . 228
21.1 Flash devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
21.1.1 21.1.2 Flash configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 Flash ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
21.2 21.3
ROM device ordering information and transfer of customer code . . . . . 232 Development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
21.3.1 21.3.2 21.3.3 21.3.4 21.3.5 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 Evaluation tools and starter kits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 Development and debugging tools . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 Programming tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 Socket and emulator adapter information . . . . . . . . . . . . . . . . . . . . . . 238
21.4
ST7 application notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
22
Known limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
22.1 All Flash and ROM devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
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Contents Unexpected reset fetch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 External interrupt missed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 Clearing active interrupts outside interrupt routine . . . . . . . . . . . . . . . 242 SCI wrong break duration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 16-bit timer PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 TIMD set simultaneously with OC interrupt . . . . . . . . . . . . . . . . . . . . . 244 I2C multimaster . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 Pull-up always active on PE2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244
22.2
Limitations specific to 44-pin 32 Kbyte ROM devices . . . . . . . . . . . . . . . 244
22.2.1 22.2.2 22.2.3 Halt/Active Halt mode power consumption with external clock enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 Active Halt power consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 IC exit from Halt/Active Halt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
23
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
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List of tables
ST72321Bxxx-Auto
List of tables
Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Table 45. Table 46. Table 47. Table 48. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Device pin description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Sectors available in Flash devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Flash control/status register address and reset value . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Arithmetic management bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Interrupt management bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Interrupt software priority selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 ST7 clock sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Effect of low power modes on SI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 AVD interrupt control/wake-up capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 SICSR description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Reset source flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Interrupt software priority levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 CPU CC register interrupt bits description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Interrupt software priority levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Interrupt priority bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Interrupt dedicated instruction set. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Interrupt mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 EICR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Interrupt sensitivity - ei2 (port B3..0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Interrupt sensitivity - ei3 (port B7..4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Interrupt sensitivity - ei0 (port A3..0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Interrupt sensitivity - ei1 (port F2..0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Nested interrupts register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 MCC/RTC low power mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 I/O output mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 I/O port mode options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 I/O port configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 I/O port configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Effect of low power modes on I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 I/O port interrupt control/wake-up capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 I/O port register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Effect of low power modes on WDG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 WDGCR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Watchdog timer register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Effect of low power modes on MCC/RTC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 MCC/RTC interrupt control/wake-up capability. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 MCCSR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Time base selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 MCCBCR register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Beep frequency selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Main clock controller register map and reset values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 ARTCSR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Prescaler selection for ART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 ARTCAR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 ARTAAR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 PWM frequency versus resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
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ST72321Bxxx-Auto Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. Table 58. Table 59. Table 60. Table 61. Table 62. Table 63. Table 64. Table 65. Table 66. Table 67. Table 68. Table 69. Table 70. Table 71. Table 72. Table 73. Table 74. Table 75. Table 76. Table 77. Table 78. Table 79. Table 80. Table 81. Table 82. Table 83. Table 84. Table 85. Table 86. Table 87. Table 88. Table 89. Table 90. Table 91. Table 92. Table 93. Table 94. Table 95. Table 96. Table 97. Table 98. Table 99. Table 100.
List of tables
PWMCR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 PWM output signal polarity selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 PWMDCRx register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 ARTICCSR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 ARTICRx register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 PWM auto-reload timer register map and reset values. . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Effect of low power modes on 16-bit timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 16-bit timer interrupt control/wake-up capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 Timer modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 CR1 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 CR2 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 Timer clock selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 CSR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 16-bit timer register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 Effect of low power modes on SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 SPI interrupt control/wake-up capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 SPICR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 SPI master mode SCK frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 SPICSR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 SPI register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 Frame formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 Effect of low power modes on SCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 SCI interrupt control/wake-up capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 SCISR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 SCICR1 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 SCICR2 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 SCIBRR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 SCIERPR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 SCIETPR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 Baud rate selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 SCI register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 Effect of low power modes on I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 I2C interrupt control/wake-up capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 CR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 SR1 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 SR2 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 CCR register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 DR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 OAR1 register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 OAR2 register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 I2C register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 Effect of low power modes on ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 ADCCSR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 ADCDRH register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 ADCDRL register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 ADC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 Addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 CPU addressing mode overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 Inherent instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 Immediate instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 Instructions supporting direct, indexed, indirect, and indirect indexed addressing modes 185 Available relative direct/indirect instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
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List of tables Table 101. Table 102. Table 103. Table 104. Table 105. Table 106. Table 107. Table 108. Table 109. Table 110. Table 111. Table 112. Table 113. Table 114. Table 115. Table 116. Table 117. Table 118. Table 119. Table 120. Table 121. Table 122. Table 123. Table 124. Table 125. Table 126. Table 127. Table 128. Table 129. Table 130. Table 131. Table 132. Table 133. Table 134. Table 135. Table 136. Table 137. Table 138. Table 139. Table 140. Table 141. Table 142. Table 143. Table 144. Table 145. Table 146. Table 147. Table 148. Table 149. Table 150.
ST72321Bxxx-Auto
Instruction groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 Instruction set overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 Operating conditions with low voltage detector (LVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 Auxiliary voltage detector (AVD) thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 External voltage detector (EVD) thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 Current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 Oscillators, PLL and LVD current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 On-chip peripherals current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 General timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 External clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 Crystal and ceramic resonator oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 OSCRANGE selection for typical resonators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 RC oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 RAM supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 Dual voltage HDFlash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 EMS test results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 EMI emissions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 I/O port pin general characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 Output driving current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 Asynchronous RESET pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 ICCSEL/VPP pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 8-bit PWM-ART auto-reload timer characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 16-bit timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 I2C control interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 SCL frequency table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 10-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 64-pin (14x14) low profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . 224 64-pin (10x10) low profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . 225 44-pin (10x10) low profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . 226 Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 Soldering compatibility (wave and reflow soldering process) . . . . . . . . . . . . . . . . . . . . . . 227 Flash option bytes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 Option byte 0 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 Option byte 1 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 Package selection (OPT7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 Flash user programmable device types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 FASTROM factory coded device types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 ROM factory coded device types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 STMicroelectronics development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238 Suggested list of socket types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
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ST72321Bxxx-Auto
List of figures
List of figures
Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. Figure 42. Figure 43. Figure 44. Figure 45. Figure 46. Figure 47. Figure 48. Device block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 64-pin LQFP 14x14 and 10x10 package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 44-pin LQFP package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Memory map and sector address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Typical ICC interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 CPU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Stack manipulation example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Clock, reset and supply block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 PLL block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Reset block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 RESET sequence phases. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 RESET sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Low voltage detector versus reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Using the AVD to monitor VDD (AVDS bit = 0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Using the voltage detector to monitor the EVD pin (AVDS bit = 1). . . . . . . . . . . . . . . . . . . 52 Interrupt processing flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Priority decision process flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Concurrent interrupt management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Nested interrupt management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 External interrupt control bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Power saving mode transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Slow mode clock transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Wait mode flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Active Halt timing overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Active Halt mode flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Halt timing overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Halt mode flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 I/O port general block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Interrupt I/O port state transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Watchdog block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Approximate timeout duration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Exact timeout duration (tmin and tmax) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Main clock controller (MCC/RTC) block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 PWM auto-reload timer block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Output compare control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 PWM auto-reload timer function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 PWM signal from 0% to 100% duty cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 External event detector example (3 counts) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Input capture timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Timer block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 16-bit read sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 Counter timing diagram, internal clock divided by 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 Input capture block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Input capture timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Output compare block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
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List of figures Figure 49. Figure 50. Figure 51. Figure 52. Figure 53. Figure 54. Figure 55. Figure 56. Figure 57. Figure 58. Figure 59. Figure 60. Figure 61. Figure 62. Figure 63. Figure 64. Figure 65. Figure 66. Figure 67. Figure 68. Figure 69. Figure 70. Figure 71. Figure 72. Figure 73. Figure 74. Figure 75. Figure 76. Figure 77. Figure 78. Figure 79. Figure 80. Figure 81. Figure 82. Figure 83. Figure 84. Figure 85. Figure 86. Figure 87. Figure 88. Figure 89. Figure 90. Figure 91. Figure 92. Figure 93. Figure 94. Figure 95. Figure 96. Figure 97. Figure 98. Figure 99. Figure 100.
ST72321Bxxx-Auto
Output compare timing diagram, fTIMER = fCPU/2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 Output compare timing diagram, fTIMER = fCPU/4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 One pulse mode cycle flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 One pulse mode timing example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 Pulse width modulation mode timing example with 2 output compare functions . . . . . . . 115 Pulse width modulation cycle flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 Serial peripheral interface block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 Single master/single slave application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 Generic SS timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 Hardware/Software slave select management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 Data clock timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 Clearing the WCOL bit (Write Collision Flag) software sequence . . . . . . . . . . . . . . . . . . 134 Single master / multiple slave configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 SCI block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 Word length programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 SCI baud rate and extended prescaler block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 Bit sampling in reception mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 I2C bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 I2C interface block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 Transfer sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 Interrupt control logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 ADC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 fCPU max versus VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 Typical application with an external clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 Typical application with a crystal or ceramic resonator. . . . . . . . . . . . . . . . . . . . . . . . . . . 200 Application with a crystal or ceramic resonator for ROM (LQFP64 or any 48/60K ROM) 201 Typical fOSC(RCINT) versus TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 Integrated PLL jitter versus signal frequency(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 Unused I/O pins configured as input. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 Typical IPU vs VDD with VIN = VSS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 Typical VOL at VDD = 5V (standard) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 Typical VOL at VDD = 5V (high-sink) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 Typical VOH at VDD = 5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 Typical VOL versus VDD (standard). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 Typical VOL versus VDD (high-sink) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 Typical VDD-VOH versus VDD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 RESET pin protection when LVD is enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 RESET pin protection when LVD is disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 Two typical applications with ICCSEL/VPP pin(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 SPI slave timing diagram with CPHA = 0(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 SPI slave timing diagram with CPHA = 1(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 SPI master timing diagram(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 Typical application with I2C BUS and timing diagram(1) . . . . . . . . . . . . . . . . . . . . . . . . . 219 RAIN maximum versus fADC with CAIN = 0pF(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 Recommended CAIN and RAIN values(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 Typical A/D converter application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 Power supply filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 ADC error classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 64-pin (14x14) low profile quad flat package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 64-pin (10x10) low profile quad flat package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
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ST72321Bxxx-Auto Figure 101. Figure 102. Figure 103. Figure 104.
List of figures
44-pin (10x10) low profile quad flat package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 Flash commercial product code structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 FASTROM commercial product code structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 ROM commercial product code structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
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Introduction
ST72321Bxxx-Auto
1
1.1
Introduction
Description
The ST72F321B-Auto Flash and ST72321B-Auto ROM devices are members of the ST7 microcontroller family designed for mid-range automotive applications. Different package options offer up to 48 I/O pins. All devices are based on a common industry-standard 8-bit core, featuring an enhanced instruction set and are available with Flash or ROM program memory. The ST7 family architecture offers both power and flexibility to software developers, enabling the design of highly efficient and compact application code. The on-chip peripherals include an A/D converter, a PWM autoreload timer, two general purpose timers, a watchdog timer, a real-time base main clock controller, I2C, SPI and SCI interfaces. For power economy, the microcontroller can switch dynamically into Wait, Slow, Active Halt or Halt mode when the application is in idle or standby state. Typical applications include

all types of car body applications such as window lift, DC motor control, rain sensors safety microcontroller in airbag and engine management applications auxiliary functions in car radios
Related documentation Migrating applications from ST72511/311/314 to ST72521/321/324 (AN1131)
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ST72321Bxxx-Auto Figure 1. Device block diagram
Introduction
8-BIT CORE ALU RESET VPP TLI VSS VDD EVD OSC1 OSC2 CONTROL
PROGRAM MEMORY (32 - 60 Kbytes) RAM (1024 - 2048 bytes)
LVD AVD WATCHDOG OSC I2C PORT A PORT B PB7:0 (8-bits) PWM ART PORT C TIMER B SCI SPI PORT D PC7:0 (8-bits) ADDRESS AND DATA BUS MCC/RTC/BEEP PA7:0 (8-bits)
PORT F PF7:0 (8-bits) TIMER A BEEP PORT E PE7:0 (8-bits)
PD7:0 (8-bits) 10-BIT ADC VAREF VSSA
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Introduction
ST72321Bxxx-Auto
1.2
Differences between ST72321B-Auto and ST72321B datasheets
The following sections list the differences between the ST72321B-Auto datasheet (version 1) and the ST72321B datasheet (version 4 dated 10 April 2007).
1.2.1
Principal differences
1. Table 2: Device pin description on page 28: - - - - 2. - - 3. - - - - - 4. 5. removed LQFP32 added caution text for PC6 replaced VREF with VAREF in Note 3 added Note 4 to LQFP44 pin No. 22 modified Input and Output table headers changed configuration of pin PE2 and modified Note 1 changed maximum value for output current sunk by any standard I/O and control pin changed maximum value for output current sunk by any high sink I/O pin added "Injected current on PC6 pin (Flash devices only)" to IINJ(PIN) ratings reorganized footnotes modified Note 3
Table 30: I/O port configuration on page 79:
Table 104: Current characteristics on page 192:
Table 110: Current consumption on page 196: Changed Flash device typical and maximum values in Active Halt mode Table 120: Dual voltage HDFlash memory on page 203: - - changed data retention conditions and minimum value replaced TA=25C with TA=85C in conditions for NRW modified parameter for input leakage current removed negative input leakage current parameter added Note 2 added maximum values specific to 32 Kbyte Flash devices only added conditions to total unadjusted error, to offset error and to gain error redistributed footnotes modified Note 1 Option byte 0: Changed OPT1 to reserved Option byte 1: Replaced OPT7 default value with Note 1 Option byte 1: Changed OPT3 default value of from 1 to 0
6.
Table 134: 10-bit ADC characteristics on page 220: - - -
7.
Table 135: ADC accuracy on page 223 - - - -
8.
Table 141: Flash option bytes on page 228: - - -
9.
Table 142: Option byte 0 bit description on page 228: Changed OPT1 to reserved
10. Table 143: Option byte 1 bit description on page 229: Modified function description for OPT3:1
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ST72321Bxxx-Auto 11. Table 144: Package selection (OPT7) on page 230: Removed K version
Introduction
12. ST72321B-Auto MIcrocontroller FASTROM/ROM Option List on page 236: - - - updated to include only automotive devices added notes 1 and 2 to PLL option added caution about readout protection binary value being inverted between ROM and Flash products
1.2.2
Minor content differences
1. ST72321Bxxx-Auto on page 1: - - 2. - - - - 3. 4. changed document title and description removed LQFP32 package outline modified data retention in Memories replaced `up to 16 robust input ports' with `up to 16 input ports' in 1 analog peripheral (low current coupling) removed Instruction set from list modified Development tools list
Features on page 1:
Section 1.1: Description on page 18: Edited content Figure 3: 44-pin LQFP package pinout on page 27: - - added Note 1 for pin 22 aligned names of pins 2, 3, 4, 5 and 6 to those in Table 2
5. 6.
Section 2.1: Package pinout: Removed figure 32-pin LQFP package pinout Table 8: Interrupt software priority selection on page 42 - - - - removed footnote link from PA6 and PA7 alternate functions cells - linked Note 1 to unbonded I/O pins in LQFP44 column - defined pin EVD as type `I' and as input level `A'
7. 8.
Table 8: Interrupt software priority selection on page 42: Added `level' column Section 9.3: I/O port implementation on page 79: Removed following five tables: - - - - - Standard ports PA5:4, PC7:0, PD7:0, PE7:3, PE1:0, PF7:3 Interrupt ports PA2:0, PB6:5, PB4, PB2:0, PF1:0 (with pull-up) Interrupt ports PA3, PB7, PB3, PF2 (without pull-up) True open drain ports PA7:6 Pull-up input port PE2 (configurations already exist in Table 30: I/O port configuration on page 79)
9.
Master mode operation on page 129: Modified text concerning SPI operation
10. Section 17.3.2: Starting the conversion on page 178: Replaced `A read to the ADCDRH resets the EOC bit' with `A read to the ADCDRH or a write to any bit of the ADCCSR register resets the EOC bit' 11. Table 106: General operating conditions on page 193: - - - modified TA conditions to include only automotive temperature versions added Note 1 modified Note 2
12. Table 115: Crystal and ceramic resonator oscillators on page 200:
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Introduction - - - - - - - - - - added Note 3 added title removed footnote detailing SMD- and LEAD-devices removed LQFP32 from conditions added Note 1 removed footnote 2 added 32/48/60 Kbyte Flash/LQFP64 configuration added 48/60 Kbyte ROM/LQFP44 configuration added 32/48 Kbyte ROM/LQFP64 configuration changed values for 60 Kbyte ROM devices
ST72321Bxxx-Auto
13. Table 116: OSCRANGE selection for typical resonators on page 201:
14. Table 121: EMS test results on page 205:
15. Table 122: EMI emissions on page 205:
16. Section 19.7.3: Absolute maximum ratings (electrical sensitivity) on page 206: Removed text concerning dynamic latch-up (DLU) 17. Electrostatic discharge (ESD) on page 206: Replaced "JESD22-A114A/A115A standard" with "AEC-Q100-002/-003/-011 standard" in last sentence 18. Table 123: ESD absolute maximum ratings on page 206: - - - - - - - - - - added AEC-Q100 standards to conditions added `Class' column added CDM updated LU content deleted DLU content updated LU conditions and class removed DLU row replaced symbol for input leakage current IL with Ilkg modified Note 4 Added Note 5
19. Static latch-up (LU) on page 206:
20. Table 124: Electrical sensitivities on page 206:
21. Table 125: I/O port pin general characteristics on page 207:
22. Table 136: 64-pin (14x14) low profile quad flat package mechanical data on page 224: Changed dimensions in mm from 2 to 3 decimal digits and changed dimensions in inches from 3 to 4 decimal digits 23. Table 137: 64-pin (10x10) low profile quad flat package mechanical data on page 225: Changed dimensions in mm from 2 to 3 decimal digits and changed dimensions in inches from 3 to 4 decimal digits 24. Table 138: 44-pin (10x10) low profile quad flat package mechanical data on page 226: Changed dimensions in mm from 2 to 3 decimal digits and changed dimensions in inches from 3 to 4 decimal digits 25. Added Section 20.3.1: Compatibility on page 227 26. Chapter 21: Device configuration and ordering information on page 228: Reorganized subsections and made minor text editing changes 27. Table 139: Thermal characteristics on page 227:
22/247
ST72321Bxxx-Auto - - - - removed LQFP32 package reorganized order of Note 1 and Note 2 updated to include only automotive device order codes added Note 1
Introduction
28. Table 145: Flash user programmable device types on page 231:
29. Added Figure 102: Flash commercial product code structure on page 231 30. Section 21.2: ROM device ordering information and transfer of customer code on page 232: Edited and updated content 31. Added Table 146: FASTROM factory coded device types on page 232 32. Added Figure 103: FASTROM commercial product code structure on page 233 33. Added Table 147: ROM factory coded device types on page 234 34. Figure 104: ROM commercial product code structure on page 235: Updated to include only automotive devices 35. Section 21.3: Development tools on page 237: Edited and updated content 36. Table 148: STMicroelectronics development tools on page 238: Removed K devices from supported products 37. Table 149: Suggested list of socket types on page 238: Removed LQFP32 device 38. Section 21.4: ST7 application notes on page 238: Removed table ST7 application notes 39. Chapter 22: Known limitations on page 239: - - - removed section ADC accuracy 32 Kbyte Flash devices updated workaround in Section 22.1.6: TIMD set simultaneously with OC interrupt on page 244 added Section 22.2: Limitations specific to 44-pin 32 Kbyte ROM devices on page 244
1.2.3
Editing and formatting differences
1. 2. 3. 4. 5. 6. 7. 8. 9. Reformatted document Table 1: Device summary on page 1: Updated to include only automotive specific devices Section 1.1: Description on page 18: Edited content Section 4.6: IAP (in-application programming) on page 39: Removed text concerning possibility to download code from USB and CAN interfaces Section 5.3.4: Condition code (CC) register on page 41: Replaced IxSPR with ISPRx Table 7: Interrupt management bits on page 42: Modified bit names Monitoring the VDD main supply on page 50: Edited bullet text at end of section Table 10: Effect of low power modes on SI on page 52: Added title Table 11: AVD interrupt control/wake-up capability on page 52: Added title
10. Table 13: Reset source flags on page 53: Added title 11. Figure 18: Priority decision process flowchart on page 56: Changed title 12. Table 15: CPU CC register interrupt bits description on page 59: Modified bit names 13. Table 17: Interrupt priority bits on page 60: Added title 14. Table 26: MCC/RTC low power mode selection on page 70: Added title
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Introduction 15. Table 27: I/O output mode selection on page 76: Added title
ST72321Bxxx-Auto
16. Table 31: Effect of low power modes on I/O ports on page 80: Added title 17. Table 32: I/O port interrupt control/wake-up capability on page 80: Added title 18. Table 34: Effect of low power modes on WDG on page 85: Added title 19. Table 37: Effect of low power modes on MCC/RTC on page 88: Added title 20. Table 38: MCC/RTC interrupt control/wake-up capability on page 88: Added title 21. Table 40: Time base selection on page 90: Added title 22. Table 42: Beep frequency selection on page 90: Added title 23. Table 45: Prescaler selection for ART on page 98: Added title 24. Table 50: PWM output signal polarity selection on page 100: Added title 25. 16-bit read sequence on page 106: Minor text editing changes 26. Section 13.3.6: One Pulse mode on page 113: Edited step 1 of procedure 27. Section 13.3.7: Pulse width modulation mode on page 115: Edited steps 1 and 2 of procedure 28. Table 55: Effect of low power modes on 16-bit timer on page 117: Added title 29. Table 56: 16-bit timer interrupt control/wake-up capability on page 117: Added title 30. Table 63: Effect of low power modes on SPI on page 135: Added title 31. Table 64: SPI interrupt control/wake-up capability on page 135: Added title 32. Table 70: Effect of low power modes on SCI on page 151: Added title 33. Table 71: SCI interrupt control/wake-up capability on page 151: Added title 34. Table 80: Effect of low power modes on I2C on page 168: Added title 35. Figure 69: Interrupt control logic diagram on page 168: Changed title 36. Table 81: I2C interrupt control/wake-up capability on page 168: Added title 37. Table 90: Effect of low power modes on ADC on page 179: Changed title 38. Table 103: Voltage characteristics on page 191: Removed note 2 39. Removed note below Figure 73: fCPU max versus VDD on page 193 40. Table 111: Oscillators, PLL and LVD current consumption on page 197: Added title 41. Table 114: External clock source on page 199: Replaced symbol for input leakage current IL with Ilkg 42. Figure 74: Typical application with an external clock source on page 199: Replaced symbol IL with Ilkg 43. Section 19.7: EMC (electromagnetic compatibility) characteristics on page 204: Modified title 44. Table 128: ICCSEL/VPP pin characteristics on page 213: Replaced symbol for input leakage current IL with Ilkg 45. Table 131: SPI characteristics on page 215: Added Note 1 46. Figure 90: SPI slave timing diagram with CPHA = 0(1) on page 216: Reorganized footnotes 47. Figure 91: SPI slave timing diagram with CPHA = 1(1) on page 216: Reorganized footnotes 48. Figure 92: SPI master timing diagram(1) on page 217: Reorganized footnotes 49. Table 132: I2C control interface characteristics on page 218: Reorganized footnotes
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ST72321Bxxx-Auto
Introduction
50. Figure 93: Typical application with I2C BUS and timing diagram(1) on page 219: Reorganized footnotes 51. Figure 96: Typical A/D converter application on page 221: - - replaced symbol IL with Ilkg removed Ilkg value `1A'
52. Figure 98: ADC error classification on page 223: Changed title 53. Table 136: 64-pin (14x14) low profile quad flat package mechanical data on page 224: Added Note 1 54. Table 137: 64-pin (10x10) low profile quad flat package mechanical data on page 225: Added Note 1
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Package pinout and pin description
ST72321Bxxx-Auto
2
2.1
Figure 2.
Package pinout and pin description
Package pinout
64-pin LQFP 14x14 and 10x10 package pinout
(HS) PE4 (HS) PE5 (HS) PE6 (HS) PE7 PWM3 / PB0 PWM2 / PB1 PWM1 / PB2 PWM0 / PB3 ARTCLK / (HS) PB4 ARTIC1 / PB5 ARTIC2 / PB6 PB7 AIN0 / PD0 AIN1 / PD1 AIN2 / PD2 AIN3 / PD3
64 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
PE3 PE2 PE1 / RDI PE0 / TDO VDD_2 OSC1 OSC2 VSS_2 TLI EVD RESET VPP / ICCSEL PA7 (HS) / SCLI PA6 (HS) / SDAI PA5 (HS) PA4 (HS)
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 ei0 44 43 ei2 42 41 40 39 ei3 38 37 36 35 ei1 34 33 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
VSS_1 VDD_1 PA3 (HS) PA2 PA1 PA0 PC7 / SS / AIN15 PC6 / SCK / ICCCLK PC5 / MOSI / AIN14 PC4 / MISO / ICCDATA PC3 (HS) / ICAP1_B PC2 (HS) / ICAP2_B PC1 / OCMP1_B / AIN13 PC0 / OCMP2_B / AIN12 VSS_0 VDD_0
26/247
AIN4 / PD4 AIN5 / PD5 AIN6 / PD6 AIN7 / PD7 VAREF VSSA VDD_3 VSS_3 MCO / AIN8 / PF0 BEEP / (HS) PF1 (HS) PF2 OCMP2_A / AIN9 / PF3 OCMP1_A / AIN10 / PF4 ICAP2_A / AIN11 / PF5 ICAP1_A / (HS) PF6 EXTCLK_A / (HS) PF7
(HS) 20mA high sink capability eix associated external interrupt vector
ST72321Bxxx-Auto Figure 3. 44-pin LQFP package pinout
Package pinout and pin description
RDI / PE1 PWM3 / PB0 PWM2 / PB1 PWM1 / PB2 PWM0 / PB3 ARTCLK / (HS) PB4 AIN0 / PD0 AIN1 / PD1 AIN2 / PD2 AIN3 / PD3 AIN4 / PD4
44 43 42 41 40 39 38 37 36 35 34 1 33 2 32 3 31 ei0 ei2 4 30 5 29 ei3 6 28 7 27 8 26 9 25 ei1 10 24 11 23 12 13 14 15 16 17 18 19 20 21 22
PE0 / TDO VDD_2 OSC1 OSC2 VSS_2 RESET VPP / ICCSEL PA7 (HS) / SCLI PA6 (HS) / SDAI PA5 (HS) PA4 (HS) VSS_1 VDD_1 PA3 (HS) PC7 / SS / AIN15 PC6 / SCK / ICCCLK PC5 / MOSI / AIN14 PC4 / MISO / ICCDATA PC3 (HS) / ICAP1_B PC2 (HS) / ICAP2_B PC1 / OCMP1_B / AIN13 PC0 / OCMP2_B / AIN12 AIN5 / PD5 VAREF VSSA MCO / AIN8 / PF0 BEEP / (HS) PF1 (HS) PF2 OCMP1_A / AIN10 / PF4 ICAP1_A / (HS) PF6 EXTCLK_A / (HS) PF7 VDD_0 VSS_0(1)
(HS) 20mA high sink capability eix associated external interrupt vector
1. Pin 22 is not connected on 48 Kbyte and 64 Kbyte ROM devices
For external pin connection guidelines, refer to Chapter 19: Electrical characteristics.
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Package pinout and pin description
ST72321Bxxx-Auto
2.2
Pin description
In the device pin description table, the RESET configuration of each pin is shown in bold. This configuration is valid as long as the device is in reset state. Refer to Chapter 9: I/O ports on page 75 for more details on the software configuration of the I/O ports.
Table 2.
Pin No. LQFP64 LQFP44
Device pin description
Level Type Input Pin name Output Input float wpu ana int Port Output OD PP Main function (after reset)
Alternate function
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
(1)(2)
PE4(HS) PE5(HS) PE6(HS) PE7(HS) PB0/PWM3 PB1/PWM2 PB2/PWM1 PB3/PWM0
I/O CT I/O CT I/O CT I/O CT I/O CT I/O CT I/O CT I/O CT
HS HS HS HS
X X X X X X X X
X X X X ei2 ei2 ei2 ei2 ei3 ei3 ei3 ei3 X X X X X X X X X X X X X X X X
X X X X X X X X X X X X X X X X X X X X
X X X X X X X X X X X X X X X X X X X X
Port E4 Port E5 Port E6 Port E7 Port B0 Port B1 Port B2 Port B3 Port B4 Port B5 Port B6 Port B7 Port D0 Port D1 Port D2 Port D3 Port D4 Port D5 Port D6 Port D7 ADC Analog Input 0 ADC Analog Input 1 ADC Analog Input 2 ADC Analog Input 3 ADC Analog Input 4 ADC Analog Input 5 ADC Analog Input 6 ADC Analog Input 7 PWM Output 3 PWM Output 2 PWM Output 1 PWM Output 0 PWM-ART External Clock PWM-ART Input Capture 1 PWM-ART Input Capture 2
(1)(2)
(1)(2)
(1)(2)
2 3 4 5 6 (1)(2)
PB4(HS)/ARTCLK I/O CT PB5 / ARTIC1 PB6 / ARTIC2 PB7 PD0/AIN0 PD1/AIN1 PD2/AIN2 PD3/AIN3 PD4/AIN4 PD5/AIN5 PD6/AIN6 PD7/AIN7 I/O CT I/O CT I/O CT I/O CT I/O CT I/O CT I/O CT I/O CT I/O CT I/O CT I/O CT
HS
X X X X X X X X X X X X
(1)(2)
(1)(2)
7 8 9 10 11 12 (1)(2)
(2)(1)
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ST72321Bxxx-Auto Table 2.
Pin No. LQFP64 LQFP44 Type Pin name
Package pinout and pin description
Device pin description (continued)
Level Output Input Input float wpu ana int Port Output OD PP Main function (after reset)
Alternate function
21 22 23 24 25 26 27 28
13 14 15 16 17 (1)(2)
VAREF(3) VSSA(3) VDD_3
(3)
I S S S I/O CT I/O CT I/O CT I/O CT HS HS X X X X X ei1 ei1 ei1 X X X X X X X X X X
Analog Reference Voltage for ADC Analog Ground Voltage Digital Main Supply Voltage Digital Ground Voltage Port F0 Port F1 Port F2 Port F3 Timer A Output Compare 2 Timer A Output Compare 1 Timer A Input Capture 2 ADC Analog Input 9 ADC Analog Input 10 ADC Analog Input 11 ADC Main clock Analog out (fOSC/2) Input 8 Beep signal output
VSS_3(3) PF0/MCO/AIN8 PF1 (HS)/BEEP PF2 (HS) PF3/OCMP2_A/ AIN9 PF4/OCMP1_A/ AIN10 PF5/ICAP2_A/ AIN11
29
18
I/O CT
X
X
X
X
X
Port F4
30 31 32 33 34 35
(1)(2)
I/O CT HS HS
X X X
X X X
X
X X X
X X X
Port F5 Port F6 Port F7
19 20 21 22(4) 23
PF6(HS)/ICAP1_A I/O CT PF7(HS)/ EXTCLK_A VDD_0(3) VSS_0
(3)
Timer A Input Capture 1 Timer A External Clock Source
I/O CT S S I/O CT
Digital Main Supply Voltage Digital Ground Voltage X X X X X Port C0 Timer B Output Compare 2 Timer B Output Compare 1 ADC Analog Input 12 ADC Analog Input 13
PC0/OCMP2_B/ AIN12 PC1/OCMP1_B/ AIN13 PC2(HS)/ ICAP2_B PC3(HS)/ ICAP1_B PC4/MISO/ ICCDATA
36
24
I/O CT
X
X
X
X
X
Port C1
37 38
25 26
I/O CT I/O CT
HS HS
X X
X X
X X
X X
Port C2 Port C3
Timer B Input Capture 2 Timer B Input Capture 1 SPI Master In / Slave Out Data SPI Master Out / Slave In Data ICC Data Input ADC Analog Input 14
39
27
I/O CT
X
X
X
X
Port C4
40
28
PC5/MOSI/AIN14
I/O CT
X
X
X
X
X
Port C5
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Package pinout and pin description Table 2.
Pin No. LQFP64 LQFP44 Type Pin name
ST72321Bxxx-Auto
Device pin description (continued)
Level Output Input Input float wpu ana int Port Output OD PP Main function (after reset)
Alternate function
SPI Serial Clock 41 29 PC6/SCK/ICCCLK I/O CT X X X X Port C6
ICC Clock Output
Caution: Negative current injection not allowed on this pin (Flash devices only) SPI Slave Select (active low) ADC Analog Input 15
42
30 (1)(2)
PC7/SS/AIN15
I/O CT
X
X
X
X
X
Port C7
43 44 45 46 47 48 49 50 51 52
PA0 PA1 PA2 PA3(HS) VDD_1
(3)
I/O CT I/O CT I/O CT I/O CT S S I/O CT I/O CT I/O CT I/O CT HS HS HS HS HS
X X X X
ei0 ei0 ei0 ei0
X X X X
X X X X
Port A0 Port A1 Port A2 Port A3 Digital Main Supply Voltage Digital Ground Voltage
(2)(1)
(1)(2)
31 32 33 34 35 36 37
VSS_1(3) PA4(HS) PA5(HS) PA6(HS)/SDAI PA7(HS)/SCLI
X X X X
X X
X X T T
X X
Port A4 Port A5 Port A6 Port A7 I2C Data I2C Clock
53
38
VPP/ ICCSEL
I
Must be tied low. In Flash programming mode, this pin acts as the programming voltage input VPP. See Section 19.9.2: ICCSEL/VPP pin for more details. High voltage must not be applied to ROM devices. Top priority non-maskable interrupt External voltage detector X Top level interrupt input pin Digital Ground Voltage Resonator oscillator inverter output External clock input or Resonator oscillator inverter input Digital Main Supply Voltage X X X X Port E0 SCI Transmit Data Out
54 55 56 57 58 59 60 61
39 40 41 42 43 44
RESET EVD TLI VSS_2
(3)
I/O CT I I S I/O I S I/O CT A CT
OSC2(5) OSC1(5) VDD_2(3) PE0/TDO
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ST72321Bxxx-Auto Table 2.
Pin No. LQFP64 LQFP44 Type Pin name
Package pinout and pin description
Device pin description (continued)
Level Output Input Input float wpu ana int Port Output OD PP Main function (after reset) Port E1 Port E2 Port E3
Alternate function
62 63 64 -
1
(1)
PE1/RDI PE2 PE3
I/O CT I/O CT I/O CT
X
X X
X X
(6)
X X
(6)
SCI Receive Data In
(2)(1)
X
X
X
X
1. On the chip, each I/O port may have up to 8 pads. Pads that are not bonded to external pins are in input pull-up configuration after reset. The configuration of these pads must be kept at reset state to avoid added current consumption. 2. On the chip, each I/O port may have up to eight pads. Pads that are not bonded to external pins are in input pull-up configuration after reset. The configuration of these pads must be kept at reset state to avoid added current consumption. 3. It is mandatory to connect all available VDD and VAREF pins to the supply voltage and all VSS and VSSA pins to ground. 4. Not connected in 48 Kbyte and 64 Kbyte ROM devices 5. OSC1 and OSC2 pins connect a crystal/ceramic resonator or an external source to the on-chip oscillator; see Chapter 1: Introduction on page 18 and Section 19.5: Clock and timing characteristics on page 199 for more details. 6. Pull-up always activated on PE2; see limitation Section 22.1.8: Pull-up always active on PE2 on page 244.
Legend / Abbreviations for Table 2: Type: I = input O = output S = supply A = dedicated analog input C = CMOS 0.3VDD/0.7VDD CT = CMOS 0.3VDD/0.7VDD with input trigger HS = 20mA high sink (on N-buffer only) float = floating wpu = weak pull-up int = interrupt(a) ana = analog OD = open-drain(b) PP = push-pull
Input level: In/Output level: Output level:
Port and control configuration: Input:
Output:
a. In the interrupt input column, "eiX" defines the associated external interrupt vector. If the weak pull-up column (wpu) is merged with the interrupt column (int), then the I/O configuration is pull-up interrupt input, otherwise the configuration is floating interrupt input. b. In the open-drain output column, "T" defines a true open-drain I/O (P-Buffer and protection diode to VDD are not implemented). See Chapter 9: I/O ports on page 75 and Section 19.8: I/O port pin characteristics on page 207 for more details.
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Register and memory map
ST72321Bxxx-Auto
3
Register and memory map
As shown in Figure 4, the MCU is capable of addressing 64 Kbytes of memories and I/O registers. The available memory locations consist of 128 bytes of register locations, up to 2 Kbytes of RAM and up to 60 Kbytes of user program memory. The RAM space includes up to 256 bytes for the stack from 0100h to 01FFh. The highest address bytes contain the user reset and interrupt vectors.
Caution:
Memory locations marked as "Reserved" must never be accessed. Accessing a reserved area can have unpredictable effects on the device. Related documentation Executing Code in ST7 RAM (AN 985)
Figure 4.
0000h 007Fh 0080h
Memory map
HW Registers (see Table 3)
0080h
Short Addressing RAM (zero page)
00FFh 0100h
RAM (2048, 1536 or 1024 bytes)
087Fh 0880h
256 bytes Stack
01FFh 0200h or 047Fh or 067Fh or 087Fh 1000h
Reserved
0FFFh 1000h
16-bit Addressing RAM
60 Kbytes 48 Kbytes 32 Kbytes
4000h 8000h
Program Memory (60, 48 or 32 Kbytes)
FFDFh FFE0h FFFFh
Interrupt and Reset Vectors (see Table 19)
FFFFh
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ST72321Bxxx-Auto Table 3.
Address 0000h 0001h 0002h 0003h 0004h 0005h 0006h 0007h 0008h 0009h 000Ah 000Bh 000Ch 000Dh 000Eh 000Fh 0010h 0011h 0012h to 0017h 0018h 0019h 001Ah 001Bh 001Ch 001Dh 001Eh 001Fh 0020h 0021h 0022h 0023h 0024h 0025h 0026h 0027h 0028h 0029h 002Ah 002Bh 002Ch 002Dh MCC FLASH SPI SPIDR SPICR SPICSR ISPR0 ISPR1 ISPR2 ISPR3 EICR FCSR I2CCR I2CSR1 I2CSR2 I2CCCR I2COAR1 I2COAR2 I2CDR
Register and memory map
Hardware register map
Block Port A(2) Register label PADR PADDR PAOR PBDR PBDDR PBOR PCDR PCDDR PCOR PDDR PDDDR PDOR PEDR PEDDR PEOR PFDR PFDDR PFOR Register name Port A Data Register Port A Data Direction Register Port A Option Register Port B Data Register Port B Data Direction Register Port B Option Register Port C Data Register Port C Data Direction Register Port C Option Register Port D Data Register Port D Data Direction Register Port D Option Register Port E Data Register Port E Data Direction Register Port E Option Register Port F Data Register Port F Data Direction Register Port F Option Register Reserved area (6 bytes) I2C Control Register I2C Status Register 1 I2C Status Register 2 I2C Clock Control Register I2C Own Address Register 1 I2C Own Address Register2 I2C Data Register Reserved area (2 bytes) SPI Data I/O Register SPI Control Register SPI Control/Status Register Interrupt Software Priority Register 0 Interrupt Software Priority Register 1 Interrupt Software Priority Register 2 Interrupt Software Priority Register 3 External Interrupt Control Register Flash Control/Status Register Watchdog Control Register System Integrity Control/Status Register Main Clock Control/Status Register Main Clock Controller/Beep Control Register xxh 0xh 00h FFh FFh FFh FFh 00h 00h 7Fh 000x 000xb 00h 00h R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 00h 00h 00h 00h 00h 00h 00h R/W Read only Read only R/W R/W R/W R/W Reset status 00h(1) 00h 00h 00h(1) 00h 00h 00h(1) 00h 00h 00h(1) 00h 00h 00h(1) 00h 00h 00h(1) 00h 00h Remarks R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W(2) R/W(2) R/W R/W R/W
Port B(2)
Port C
Port
D(2)
Port
E(2)
Port F(2)
I2C
ITC
WATCHDOG WDGCR SICSR MCCSR MCCBCR
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Register and memory map Table 3.
Address 002Eh to 0030h 0031h 0032h 0033h 0034h 0035h 0036h 0037h 0038h 0039h 003Ah 003Bh 003Ch 003Dh 003Eh 003Fh 0040h 0041h 0042h 0043h 0044h 0045h 0046h 0047h 0048h 0049h 004Ah 004Bh 004Ch 004Dh 004Eh 004Fh 0050h 0051h 0052h 0053h 0054h 0055h 0056h 0057h 0058h to 006Fh 0070h 0071h 0072h ADC ADCCSR ADCDRH ADCDRL TBCR2 TBCR1 TBCSR TBIC1HR TBIC1LR TBOC1HR TBOC1LR TBCHR TBCLR TBACHR TBACLR TBIC2HR TBIC2LR TBOC2HR TBOC2LR SCISR SCIDR SCIBRR SCICR1 SCICR2 SCIERPR SCIETPR TACR2 TACR1 TACSR TAIC1HR TAIC1LR TAOC1HR TAOC1LR TACHR TACLR TAACHR TAACLR TAIC2HR TAIC2LR TAOC2HR TAOC2LR
ST72321Bxxx-Auto
Hardware register map (continued)
Block Register label Register name Reserved area (3 bytes) Timer A Control Register 2 Timer A Control Register 1 Timer A Control/Status Register Timer A Input Capture 1 High Register Timer A Input Capture 1 Low Register Timer A Output Compare 1 High Register Timer A Output Compare 1 Low Register Timer A Counter High Register Timer A Counter Low Register Timer A Alternate Counter High Register Timer A Alternate Counter Low Register Timer A Input Capture 2 High Register Timer A Input Capture 2 Low Register Timer A Output Compare 2 High Register Timer A Output Compare 2 Low Register Reserved area (1 byte) Timer B Control Register 2 Timer B Control Register 1 Timer B Control/Status Register Timer B Input Capture 1 High Register Timer B Input Capture 1 Low Register Timer B Output Compare 1 High Register Timer B Output Compare 1 Low Register Timer B Counter High Register Timer B Counter Low Register Timer B Alternate Counter High Register Timer B Alternate Counter Low Register Timer B Input Capture 2 High Register Timer B Input Capture 2 Low Register Timer B Output Compare 2 High Register Timer B Output Compare 2 Low Register SCI Status Register SCI Data Register SCI Baud Rate Register SCI Control Register 1 SCI Control Register 2 SCI Extended Receive Prescaler Register Reserved area SCI Extended Transmit Prescaler Register Reserved Area (24 bytes) Control/Status Register Data High Register Data Low Register 00h 00h 00h R/W Read only Read only 00h 00h xxxx x0xxb xxh xxh 80h 00h FFh FCh FFh FCh xxh xxh 80h 00h C0h xxh 00h x000 0000b 00h 00h --00h R/W R/W R/W Read only Read only R/W R/W Read only Read only Read only Read only Read only Read only R/W R/W Read only R/W R/W R/W R/W R/W R/W 00h 00h xxxx x0xxb xxh xxh 80h 00h FFh FCh FFh FCh xxh xxh 80h 00h R/W R/W R/W Read only Read only R/W R/W Read only Read only Read only Read only Read only Read only R/W R/W Reset status Remarks
TIMER A
TIMER B
SCI
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ST72321Bxxx-Auto Table 3.
Address 0073h 0074h 0075h 0076h 0077h 0078h 0079h 007Ah 007Bh 007Ch 007Dh 007Eh 007Fh
Register and memory map
Hardware register map (continued)
Block Register label PWMDCR3 PWMDCR2 PWMDCR1 PWMDCR0 PWMCR ARTCSR ARTCAR ARTARR ARTICCSR ARTICR1 ARTICR2 Register name PWM AR Timer Duty Cycle Register 3 PWM AR Timer Duty Cycle Register 2 PWM AR Timer Duty Cycle Register 1 PWM AR Timer Duty Cycle Register 0 PWM AR Timer Control Register Auto-Reload Timer Control/Status Register Auto-Reload Timer Counter Access Register Auto-Reload Timer Auto-Reload Register AR Timer Input Capture Control/Status Reg. AR Timer Input Capture Register 1 AR Timer Input Capture Register 1 Reserved area (2 bytes) Reset status 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h Remarks R/W R/W R/W R/W R/W R/W R/W R/W R/W Read only Read only
PWM ART
1. The contents of the I/O port DR registers are readable only in output configuration. In input configuration, the values of the I/O pins are returned instead of the DR register contents. 2. The bits associated with unavailable pins must always keep their reset value.
Legend: x = undefined, R/W = read/write
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Flash program memory
ST72321Bxxx-Auto
4
4.1
Flash program memory
Introduction
The ST7 dual voltage High Density Flash (HDFlash) is a non-volatile memory that can be electrically erased as a single block or by individual sectors and programmed on a byte-bybyte basis using an external VPP supply. The HDFlash devices can be programmed and erased off-board (plugged in a programming tool) or on-board using ICP (in-circuit programming) or IAP (in-application programming). The array matrix organization allows each sector to be erased and reprogrammed without affecting other sectors.
4.2
Main features
3 Flash programming modes: - - - Insertion in a programming tool. In this mode, all sectors including option bytes can be programmed or erased. ICP (in-circuit programming). In this mode, all sectors including option bytes can be programmed or erased without removing the device from the application board. IAP (in-application programming). In this mode, all sectors except Sector 0 can be programmed or erased without removing the device from the application board and while the application is running.

ICT (in-circuit testing) for downloading and executing user application test patterns in RAM Readout protection Register Access Security System (RASS) to prevent accidental programming or erasing
4.3
Structure
The Flash memory is organized in sectors and can be used for both code and data storage. Depending on the overall Flash memory size in the microcontroller device, there are up to three user sectors (see Table 4). Each of these sectors can be erased independently to avoid unnecessary erasing of the whole Flash memory when only a partial erasing is required. Table 4. Sectors available in Flash devices
Flash size (bytes) 4K 8K > 8K Available sectors Sector 0 Sectors 0, 1 Sectors 0, 1, 2
The first two sectors have a fixed size of 4 Kbytes (see Figure 5). They are mapped in the upper part of the ST7 addressing space so the reset and interrupt vectors are located in Sector 0 (F000h-FFFFh).
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ST72321Bxxx-Auto Figure 5.
4K 1000h 3FFFh 7FFFh 9FFFh BFFFh D7FFh DFFFh EFFFh FFFFh 2 Kbytes 8 Kbytes 16 Kbytes 4 Kbytes 4 Kbytes 24 Kbytes
Flash program memory Memory map and sector address
8K 10K 16K 24K 32K 48K 60K FLASH MEMORY SIZE
SECTOR 2 40 Kbytes 52 Kbytes SECTOR 1 SECTOR 0
4.3.1
Readout protection
Readout protection, when selected, provides a protection against program memory content extraction and against write access to Flash memory. Even if no protection can be considered as totally unbreakable, the feature provides a very high level of protection for a general purpose microcontroller. In Flash devices, this protection is removed by reprogramming the option. In this case, the entire program memory is first automatically erased and the device can be reprogrammed. Readout protection selection depends on the device type:

In Flash devices it is enabled and removed through the FMP_R bit in the option byte. In ROM devices it is enabled by mask option specified in the Option List.
Note:
4.4
ICC interface
ICC needs a minimum of 4 and up to 6 pins to be connected to the programming tool (see Figure 6). These pins are: RESET: VSS: ICCCLK: ICCDATA: ICCSEL/VPP: VDD: device reset device power supply ground ICC output serial clock pin ICC input/output serial data pin programming voltage application board power supply (optional, see Figure 6, Note 3)
OSC1 (or OSCIN): main clock input for external source (optional)
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Flash program memory Figure 6. Typical ICC interface
ST72321Bxxx-Auto
PROGRAMMING TOOL ICC CONNECTOR ICC Cable APPLICATION BOARD (See Note 3) OPTIONAL (See Note 4) ICC CONNECTOR HE10 CONNECTOR TYPE 9 10 7 8 5 6 3 4 1 2 APPLICATION RESET SOURCE See Note 2 10k APPLICATION POWER SUPPLY CL2 CL1 See Note 1 APPLICATION I/O
RESET
ICCCLK
ST7
1. If the ICCCLK or ICCDATA pins are only used as outputs in the application, no signal isolation is necessary. As soon as the programming tool is plugged to the board, even if an ICC session is not in progress, the ICCCLK and ICCDATA pins are not available for the application. If they are used as inputs by the application, isolation such as a serial resistor has to implemented in case another device forces the signal. Refer to the programming tool documentation for recommended resistor values. 2. During the ICC session, the programming tool must control the RESET pin. This can lead to conflicts between the programming tool and the application reset circuit if it drives more than 5mA at high level (push-pull output or pull-up resistor < 1K). A schottky diode can be used to isolate the application RESET circuit in this case. When using a classical RC network with R > 1K or a reset management IC with open-drain output and pull-up resistor > 1K, no additional components are needed. In all cases the user must ensure that no external reset is generated by the application during the ICC session. 3. The use of Pin 7 of the ICC connector depends on the programming tool architecture. This pin must be connected when using most ST programming tools (it is used to monitor the application power supply). Please refer to the programming tool manual. 4. Pin 9 has to be connected to the OSC1 or OSCIN pin of the ST7 when the clock is not available in the application or if the selected clock option is not programmed in the option byte. ST7 devices with multi-oscillator capability need to have OSC2 grounded in this case.
4.5
ICP (in-circuit programming)
To perform ICP the microcontroller must be switched to ICC (in-circuit communication) mode by an external controller or programming tool. Depending on the ICP code downloaded in RAM, Flash memory programming can be fully customized (number of bytes to program, program locations, or selection serial communication interface for downloading). When using an STMicroelectronics or third-party programming tool that supports ICP and the specific microcontroller device, the user needs only to implement the ICP hardware interface on the application board (see Figure 6). For more details on the pin locations, refer to the device pinout description.
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ICCSEL/VPP
ICCDATA
OSC2
OSC1
VDD
VSS
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Flash program memory
4.6
IAP (in-application programming)
This mode uses a BootLoader program previously stored in Sector 0 by the user (in ICP mode or by plugging the device in a programming tool). This mode is fully controlled by user software. This allows it to be adapted to the user application, (such as user-defined strategy for entering programming mode, choice of communications protocol used to fetch the data to be stored). For example, it is possible to download code from the serial peripheral or serial communication interface and program it in the Flash. IAP mode can be used to program any of the Flash sectors except Sector 0, which is write/erase protected to allow recovery in case errors occur during the programming operation.
4.7
Related documentation
For details on Flash programming and ICC protocol, refer to the ST7 Flash Programming Reference Manual and to the ST7 ICC Protocol Reference Manual.
4.8
Flash control/status register (FCSR)
FSCR 7 0 RW 6 0 RW 5 0 RW 4 0 RW 3 0 RW 2 0 RW Reset value: 0000 0000 (00h) 1 0 RW 0 0 RW
This register is reserved for use by programming tool software. It controls the Flash programming and erasing operations. Table 5. Flash control/status register address and reset value
Register label FCSR Reset value 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0
Address (Hex.) 0029h
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Central processing unit (CPU)
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5
5.1
Central processing unit (CPU)
Introduction
This CPU has a full 8-bit architecture and contains six internal registers allowing efficient 8bit data manipulation.
5.2
Main features

Enable executing 63 basic instructions Fast 8-bit by 8-bit multiply 17 main addressing modes (with indirect addressing mode) Two 8-bit index registers 16-bit stack pointer Low power Halt and Wait modes Priority maskable hardware interrupts Non-maskable software/hardware interrupts
5.3
CPU registers
The six CPU registers shown in Figure 7 are not present in the memory mapping and are accessed by specific instructions. Figure 7. CPU registers
7 Reset value = XXh 7 Reset value = XXh 7 Reset value = XXh 15 PCH 87 PCL 0 Program counter Reset value = reset vector @ FFFEh-FFFFh 7 0 1 1 I1 H I0 N Z C Reset value = 1 1 1 X 1 X X X 15 87 0 Stack pointer Reset value = stack higher address X = undefined value 0 X index register 0 Y index register 0 Accumulator
Condition code register
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Central processing unit (CPU)
5.3.1
Accumulator (A)
The accumulator is an 8-bit general purpose register used to hold operands and the results of the arithmetic and logic calculations as well as data manipulations.
5.3.2
Index registers (X and Y)
These 8-bit registers are used to create effective addresses or as temporary storage areas for data manipulation (the Cross-Assembler generates a precede instruction (PRE) to indicate that the following instruction refers to the Y register.) The Y register is not affected by the interrupt automatic procedures.
5.3.3
Program counter (PC)
The program counter is a 16-bit register containing the address of the next instruction to be executed by the CPU. It is made of two 8-bit registers PCL (Program Counter Low which is the LSB) and PCH (Program Counter High which is the MSB).
5.3.4
Condition code (CC) register
The 8-bit condition code register contains the interrupt masks and four flags representative of the result of the instruction just executed. This register can also be handled by the PUSH and POP instructions. These bits can be individually tested and/or controlled by specific instructions.
CC 7 1 6 1 5 I1 RW 4 H RW 3 I0 RW 2 N RW Reset value: 111x1xxx 1 Z RW 0 C RW
Table 6.
Bit Name
Arithmetic management bits
Function Half carry This bit is set by hardware when a carry occurs between bits 3 and 4 of the ALU during an ADD or ADC instructions. It is reset by hardware during the same instructions. 0: No half carry has occurred. 1: A half carry has occurred. This bit is tested using the JRH or JRNH instruction. The H bit is useful in BCD arithmetic subroutines. Negative This bit is set and cleared by hardware. It is representative of the result sign of the last arithmetic, logical or data manipulation. It is a copy of the result 7th bit. 0: The result of the last operation is positive or null. 1: The result of the last operation is negative (that is, the most significant bit is a logic 1). This bit is accessed by the JRMI and JRPL instructions.
4
H
2
N
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Central processing unit (CPU) Table 6.
Bit Name
ST72321Bxxx-Auto
Arithmetic management bits (continued)
Function Zero This bit is set and cleared by hardware. This bit indicates that the result of the last arithmetic, logical or data manipulation is zero. 0: The result of the last operation is different from zero. 1: The result of the last operation is zero. This bit is accessed by the JREQ and JRNE test instructions. Carry/borrow This bit is set and cleared by hardware and software. It indicates an overflow or an underflow has occurred during the last arithmetic operation. 0: No overflow or underflow has occurred. 1: An overflow or underflow has occurred. This bit is driven by the SCF and RCF instructions and tested by the JRC and JRNC instructions. It is also affected by the "bit test and branch", shift and rotate instructions.
1
Z
0
C
Table 7.
Bit Name 5 3
Interrupt management bits
Function Interrupt Software Priority 1 The combination of the I1 and I0 bits gives the current interrupt software priority. Interrupt Software Priority 0 The combination of the I1 and I0 bits gives the current interrupt software priority.
I1 I0
Table 8.
Interrupt software priority selection
Interrupt software priority Level Low I1 1 0 0 High 1 I0 0 1 0 1
Level 0 (main) Level 1 Level 2 Level 3 (= interrupt disable)
These two bits are set/cleared by hardware when entering in interrupt. The loaded value is given by the corresponding bits in the interrupt software priority registers (ISPRx). They can be also set/cleared by software with the RIM, SIM, IRET, HALT, WFI and PUSH/POP instructions. See Chapter 7: Interrupts on page 55 for more details.
5.3.5
Stack pointer (SP) register
7
SP 15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 1 7 6 5 4 3
Reset value: 01 FFh 2 1 0
SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 RW RW RW RW RW RW RW RW
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Central processing unit (CPU)
The stack pointer is a 16-bit register which is always pointing to the next free location in the stack. It is then decremented after data has been pushed onto the stack and incremented before data is popped from the stack (see Figure 8). Since the stack is 256 bytes deep, the 8 most significant bits are forced by hardware. Following an MCU Reset, or after a reset stack pointer instruction (RSP), the stack pointer contains its reset value (the SP7 to SP0 bits are set) which is the stack higher address. The least significant byte of the stack pointer (called S) can be directly accessed by an LD instruction. Note: When the lower limit is exceeded, the stack pointer wraps around to the stack upper limit, without indicating the stack overflow. The previously stored information is then overwritten and therefore lost. The stack also wraps in case of an underflow. The stack is used to save the return address during a subroutine call and the CPU context during an interrupt. The user may also directly manipulate the stack by means of the PUSH and POP instructions. In the case of an interrupt, the PCL is stored at the first location pointed to by the SP. The other registers are then stored in the next locations as shown in Figure 8.

When an interrupt is received, the SP is decremented and the context is pushed on the stack. On return from interrupt, the SP is incremented and the context is popped from the stack.
A subroutine call occupies two locations and an interrupt five locations in the stack area. Figure 8. Stack manipulation example
Interrupt Event PUSH Y POP Y IRET RET or RSP
CALL Subroutine @ 0100h
SP SP CC A X PCH SP PCH @ 01FFh PCL PCL PCH PCL Y CC A X PCH PCL PCH PCL SP CC A X PCH PCL PCH PCL SP PCH PCL SP
Stack Higher Address = 01FFh Stack Lower Address = 0100h
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6
6.1
Supply, reset and clock management
Introduction
The device includes a range of utility features for securing the application in critical situations (for example in case of a power brown-out), and reducing the number of external components. An overview is shown in Figure 9. For more details, refer to the dedicated parametric section.
6.2
Main features

Optional PLL for multiplying the frequency by 2 (not to be used with internal RC oscillator) Reset Sequence Manager (RSM) Multi-oscillator Clock Management (MO) - - 5 crystal/ceramic resonator oscillators 1 internal RC oscillator Main supply low voltage detection (LVD) Auxiliary voltage detector (AVD) with interrupt capability for monitoring the main supply or the EVD pin
System Integrity Management (SI) - -
Figure 9.
Clock, reset and supply block diagram
OSC2 OSC1
MULTIOSCILLATOR (MO)
fOSC
PLL (option)
fOSC2
MAIN CLOCK fCPU CONTROLLER WITH REAL-TIME CLOCK (MCC/RTC)
SYSTEM INTEGRITY MANAGEMENT RESET SEQUENCE RESET MANAGER (RSM) SICSR
AVD AVD AVD LVD S F RF IE 0 0 0 WDG RF
AVD Interrupt Request
WATCHDOG TIMER (WDG)
LOW VOLTAGE VSS VDD 0 EVD 1 DETECTOR (LVD)
AUXILIARY VOLTAGE DETECTOR (AVD)
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6.3
Phase locked loop
If the clock frequency input to the PLL is in the range 2 to 4 MHz, the PLL can be used to multiply the frequency by two to obtain an fOSC2 of 4 to 8 MHz. The PLL is enabled by option byte. If the PLL is disabled, then fOSC2 = fOSC/2.
Caution:
The PLL is not recommended for applications where timing accuracy is required (see Section 19.5.5: PLL characteristics on page 202). Figure 10. PLL block diagram
PLL x 2 fOSC /2
0 fOSC2 1 PLL OPTION BIT
6.4
Multi-oscillator (MO)
The main clock of the ST7 can be generated by three different source types coming from the multi-oscillator block:

an external source 4 crystal or ceramic resonator oscillators an internal high frequency RC oscillator
Each oscillator is optimized for a given frequency range in terms of consumption and is selectable through the option byte. The associated hardware configurations are shown in Table 9. Refer to Chapter 19: Electrical characteristics for more details. Caution: The OSC1 and/or OSC2 pins must not be left unconnected. For the purposes of Failure Mode and Effect Analysis, it should be noted that if the OSC1 and/or OSC2 pins are left unconnected, the ST7 main oscillator may start and, in this configuration, could generate an fOSC clock frequency in excess of the allowed maximum (> 16 MHz), putting the ST7 in an unsafe/undefined state. The product behavior must therefore be considered undefined when the OSC pins are left unconnected.
External clock source
In this external clock mode, a clock signal (square, sinus or triangle) with ~50% duty cycle has to drive the OSC1 pin while the OSC2 pin is tied to ground.
Crystal/ceramic oscillators
This family of oscillators has the advantage of producing a very accurate rate on the main clock of the ST7. The selection within a list of four oscillators with different frequency ranges has to be done by option byte in order to reduce consumption (refer to Section 21.1.1: Flash configuration on page 228 for more details on the frequency ranges). In this mode of the
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multi-oscillator, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and start-up stabilization time. The loading capacitance values must be adjusted according to the selected oscillator. These oscillators are not stopped during the RESET phase to avoid losing time in the oscillator start-up phase.
Internal RC oscillator
This oscillator allows a low cost solution for the main clock of the ST7 using only an internal resistor and capacitor. Internal RC oscillator mode has the drawback of a lower frequency accuracy and should not be used in applications that require accurate timing. In this mode, the two oscillator pins have to be tied to ground. Table 9. ST7 clock sources
Hardware configuration External clock
ST7 OSC1 OSC2
EXTERNAL SOURCE
Internal RC oscillator Crystal/Ceramic resonators
ST7 OSC1 OSC2
CL1
LOAD CAPACITORS
CL2
ST7 OSC1 OSC2
6.5
6.5.1
Reset sequence manager (RSM)
Introduction
The reset sequence manager includes three RESET sources as shown in Figure 11:

External RESET source pulse Internal LVD RESET (low voltage detection) Internal WATCHDOG RESET
These sources act on the RESET pin and it is always kept low during the delay phase.
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The RESET service routine vector is fixed at addresses FFFEh-FFFFh in the ST7 memory map. The basic RESET sequence consists of three phases as shown in Figure 12:

Active phase depending on the RESET source 256 or 4096 CPU clock cycle delay (selected by option byte) RESET vector fetch
Caution:
When the ST7 is unprogrammed or fully erased, the Flash is blank and the RESET vector is not programmed. For this reason, it is recommended to keep the RESET pin in low state until programming mode is entered, in order to avoid unwanted behavior. The 256 or 4096 CPU clock cycle delay allows the oscillator to stabilize and ensures that recovery has taken place from the Reset state. The shorter or longer clock cycle delay should be selected by option byte to correspond to the stabilization time of the external oscillator used in the application (see Section 21.1.1: Flash configuration on page 228). The RESET vector fetch phase duration is 2 clock cycles. Figure 11. Reset block diagram
VDD
RON RESET Filter INTERNAL RESET
PULSE GENERATOR
WATCHDOG RESET LVD RESET
Figure 12. RESET sequence phases
RESET ACTIVE PHASE INTERNAL RESET 256 or 4096 CLOCK CYCLES FETCH VECTOR
6.5.2
Asynchronous external RESET pin
The RESET pin is both an input and an open-drain output with integrated RON weak pull-up resistor. This pull-up has no fixed value but varies in accordance with the input voltage. It can be pulled low by external circuitry to reset the device. See Section 19.9: Control pin characteristics on page 211 for more details. A RESET signal originating from an external source must have a duration of at least th(RSTL)in in order to be recognized (see Figure 13). This detection is asynchronous and therefore the MCU can enter reset state even in Halt mode.
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The RESET pin is an asynchronous signal which plays a major role in EMS performance. In a noisy environment, it is recommended to follow the guidelines mentioned in Chapter 19: Electrical characteristics. If the external RESET pulse is shorter than tw(RSTL)out (see short ext. Reset in Figure 13), the signal on the RESET pin may be stretched. Otherwise the delay will not be applied (see long ext. Reset in Figure 13). Starting from the external RESET pulse recognition, the device RESET pin acts as an output that is pulled low during at least tw(RSTL)out.
6.5.3
External power-on RESET
If the LVD is disabled by option byte, to start up the microcontroller correctly, the user must ensure by means of an external reset circuit that the reset signal is held low until VDD is over the minimum level specified for the selected fOSC frequency (see Section 19.3: Operating conditions on page 193). A proper reset signal for a slow rising VDD supply can generally be provided by an external RC network connected to the RESET pin.
6.5.4
Internal low voltage detector (LVD) RESET
Two different RESET sequences caused by the internal LVD circuitry can be distinguished:

Power-on RESET Voltage drop RESET
The device RESET pin acts as an output that is pulled low when VDD < VIT+ (rising edge) or VDD < VIT- (falling edge) as shown in Figure 13. The LVD filters spikes on VDD larger than tg(VDD) to avoid parasitic resets.
6.5.5
Internal watchdog RESET
The RESET sequence generated by an internal Watchdog counter overflow is shown in Figure 13. Starting from the Watchdog counter underflow, the device RESET pin acts as an output that is pulled low during at least tw(RSTL)out.
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ST72321Bxxx-Auto Figure 13. RESET sequences
VDD VIT+(LVD) VIT-(LVD)
Supply, reset and clock management
LVD RESET
SHORT EXT. RESET
LONG EXT. RESET
WATCHDOG RESET
RUN
Active Phase
RUN
Active Phase
RUN
Active Phase
RUN
Active Phase
RUN
tw(RSTL)out th(RSTL)in
tw(RSTL)out th(RSTL)in DELAY tw(RSTL)out
EXTERNAL RESET SOURCE
RESET PIN WATCHDOG RESET WATCHDOG UNDERFLOW INTERNAL RESET (256 or 4096 TCPU) VECTOR FETCH
6.6
System integrity management (SI)
The System Integrity Management block contains the Low Voltage Detector (LVD) and Auxiliary Voltage Detector (AVD) functions. It is managed by the SICSR register.
6.6.1
Low voltage detector (LVD)
The low voltage detector function (LVD) generates a static reset when the VDD supply voltage is below a VIT- reference value. This means that it secures the power-up as well as the power-down keeping the ST7 in reset. The VIT- reference value for a voltage drop is lower than the VIT+ reference value for poweron in order to avoid a parasitic reset when the MCU starts running and sinks current on the supply (hysteresis). The LVD reset circuitry generates a reset when VDD is below: - - VIT+ when VDD is rising VIT- when VDD is falling
The LVD function is illustrated in Figure 14. The voltage threshold can be configured by option byte to be low, medium or high.
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Provided the minimum VDD value (guaranteed for the oscillator frequency) is above VIT-, the MCU can only be in two modes: - - under full software control in static safe reset
In these conditions, secure operation is always ensured for the application without the need for external reset hardware. During a low voltage detector reset, the RESET pin is held low, thus permitting the MCU to reset other devices. Note: The LVD allows the device to be used without any external RESET circuitry. If the medium or low thresholds are selected, the detection may occur outside the specified operating voltage range. Below 3.8V, device operation is not guaranteed. The LVD is an optional function which can be selected by option byte. It is recommended to make sure that the VDD supply voltage rises monotonously when the device is exiting from Reset, to ensure the application functions properly. Figure 14. Low voltage detector versus reset
VDD
Vhys VIT+ VIT-
RESET
6.6.2
Auxiliary voltage detector (AVD)
The auxiliary voltage detector function (AVD) is based on an analog comparison between a VIT-(AVD) and VIT+(AVD) reference value and the VDD main supply or the external EVD pin voltage level (VEVD). The VIT- reference value for falling voltage is lower than the VIT+ reference value for rising voltage in order to avoid parasitic detection (hysteresis). The output of the AVD comparator can be read directly by the application software through a real-time status bit (AVDF) in the SICSR register. This bit is read only.
Caution:
The AVD function is active only if the LVD is enabled through the option byte.
Monitoring the VDD main supply
This mode is selected by clearing the AVDS bit in the SICSR register. The AVD voltage threshold value is relative to the selected LVD threshold configured by option byte (see Section 21.1.1: Flash configuration on page 228). If the AVD interrupt is enabled, an interrupt is generated when the voltage crosses the VIT+(AVD) or VIT-(AVD) threshold (AVDF bit toggles).
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In the case of a drop in voltage, the AVD interrupt acts as an early warning, allowing software to shut down safely before the LVD resets the microcontroller. See Figure 15. The interrupt on the rising edge is used to inform the application that the VDD warning state is over. If the voltage rise time trv is less than 256 or 4096 CPU cycles (depending on the reset delay selected by option byte), no AVD interrupt will be generated when VIT+(AVD) is reached. If trv is greater than 256 or 4096 cycles
two AVD interrupts will be received if the AVD interrupt is enabled before the VIT+(AVD) threshold is reached: the first when the AVDIE bit is set, and the second when the threshold is reached. only one AVD interrupt will occur if the AVD interrupt is enabled after the VIT+(AVD) threshold is reached.
Figure 15. Using the AVD to monitor VDD (AVDS bit = 0)
VDD Early Warning Interrupt (Power has dropped, MCU not not yet in reset) Vhyst
VIT+(AVD) VIT-(AVD) VIT+(LVD) VIT-(LVD)
trv
VOLTAGE RISE TIME
AVDF bit
0
1
RESET VALUE
1
0
AVD INTERRUPT REQUEST IF AVDIE bit = 1 INTERRUPT PROCESS LVD RESET INTERRUPT PROCESS
Monitoring a voltage on the EVD pin
This mode is selected by setting the AVDS bit in the SICSR register. The AVD circuitry can generate an interrupt when the AVDIE bit of the SICSR register is set. This interrupt is generated on the rising and falling edges of the comparator output. This means it is generated when either one of these two events occur:

VEVD rises up to VIT+(EVD) VEVD falls down to VIT-(EVD)
The EVD function is illustrated in Figure 16. For more details, refer to Chapter 19: Electrical characteristics.
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Supply, reset and clock management Figure 16. Using the voltage detector to monitor the EVD pin (AVDS bit = 1)
VEVD
ST72321Bxxx-Auto
VIT+(EVD) VIT-(EVD)
Vhyst
AVDF
0
1
0
AVD INTERRUPT REQUEST IF AVDIE = 1 INTERRUPT PROCESS INTERRUPT PROCESS
6.6.3
Low power modes
Table 10.
Mode Wait Halt
Effect of low power modes on SI
Effect No effect on SI. AVD interrupts cause the device to exit from Wait mode. The SICSR register is frozen.
6.6.4
Interrupts
The AVD interrupt event generates an interrupt if the corresponding Enable Control Bit (AVDIE) is set and the interrupt mask in the CC register is reset (RIM instruction). Table 11. AVD interrupt control/wake-up capability
Event flag AVDF Enable control bit AVDIE Exit from Wait Yes Exit from Halt No
Interrupt event AVD event
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6.6.5
System Integrity (SI) Control/Status register (SICSR)
SICSR 7 AVDS RW 6 AVDIE RW 5 AVDF RW 4 LVDRF RW 3 Reset value: 000x 000x (00h) 2 Reserved 1 0 WDGRF RW
Table 12.
Bit Name
SICSR description
Function Voltage Detection selection This bit is set and cleared by software. Voltage Detection is available only if the LVD is enabled by option byte. 0: Voltage detection on VDD supply 1: Voltage detection on EVD pin Voltage Detector interrupt enable This bit is set and cleared by software. It enables an interrupt to be generated when the AVDF flag changes (toggles). The pending interrupt information is automatically cleared when software enters the AVD interrupt routine. 0: AVD interrupt disabled 1: AVD interrupt enabled Voltage Detector flag This read-only bit is set and cleared by hardware. If the AVDIE bit is set, an interrupt request is generated when the AVDF bit changes value. Refer to Figure 15 and to Monitoring the VDD main supply on page 50 for additional details. 0: VDD or VEVD over VIT+(AVD) threshold 1: VDD or VEVD under VIT-(AVD) threshold LVD reset flag This bit indicates that the last Reset was generated by the LVD block. It is set by hardware (LVD reset) and cleared by software (writing zero). See Table 13: Reset source flags for more details. When the LVD is disabled by OPTION BYTE, the LVDRF bit value is undefined. Reserved, must be kept cleared.
7
AVDS
6
AVDIE
5
AVDF
4
LVDRF
3:1
-
0
Watchdog reset flag This bit indicates that the last Reset was generated by the Watchdog peripheral. It is set by hardware (watchdog reset) and cleared by software (writing zero) or an WDGRF LVD Reset (to ensure a stable cleared state of the WDGRF flag when CPU starts). Combined with the LVDRF flag information, the flag description is given in Table 13.
Table 13.
Reset source flags
Reset sources External RESET pin Watchdog LVD LVDRF 0 0 1 WDGRF 0 1 X
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Application notes
The LVDRF flag is not cleared when another RESET type occurs (external or watchdog); the LVDRF flag remains set to keep trace of the original failure. In this case, software can detect a watchdog reset but cannot detect an external reset. Caution: When the LVD is not activated with the associated option byte, the WDGRF flag cannot be used in the application.
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Interrupts
7
7.1
Interrupts
Introduction
The ST7 enhanced interrupt management provides the following features:

Hardware interrupts Software interrupt (TRAP) Nested or concurrent interrupt management with flexible interrupt priority and level management: - - - - Up to 4 software programmable nesting levels Up to 16 interrupt vectors fixed by hardware 2 non-maskable events: RESET, TRAP 1 maskable Top Level event: TLI
This interrupt management is based on:

Bit 5 and bit 3 of the CPU CC register (I1:0) Interrupt software priority registers (ISPRx) Fixed interrupt vector addresses located at the high addresses of the memory map (FFE0h to FFFFh) sorted by hardware priority order
This enhanced interrupt controller guarantees full upward compatibility with the standard (not nested) ST7 interrupt controller.
7.2
Masking and processing flow
The interrupt masking is managed by the I1 and I0 bits of the CC register and the ISPRx registers which give the interrupt software priority level of each interrupt vector (see Table 14). The processing flow is shown in Figure 17. When an interrupt request has to be serviced:

Normal processing is suspended at the end of the current instruction execution. The PC, X, A and CC registers are saved onto the stack. I1 and I0 bits of CC register are set according to the corresponding values in the ISPRx registers of the serviced interrupt vector. The PC is then loaded with the interrupt vector of the interrupt to service and the first instruction of the interrupt service routine is fetched (refer to Table 19: Interrupt mapping for vector addresses).
The interrupt service routine should end with the IRET instruction which causes the contents of the saved registers to be recovered from the stack. Note: As a consequence of the IRET instruction, the I1 and I0 bits will be restored from the stack and the program in the previous level will resume.
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Interrupts Table 14. Interrupt software priority levels
Interrupt software priority Level 0 (main) Level 1 Level 2 Level 3 (= interrupt disable) High Level Low
ST72321Bxxx-Auto
I1 1 0 0 1
I0 0 1 0 1
Figure 17. Interrupt processing flowchart
RESET
PENDING INTERRUPT N
Y Interrupt has the same or a lower software priority than current one
TRAP N I1:0 Interrupt has a higher software priority than current one
Y
FETCH NEXT INSTRUCTION Y
THE INTERRUPT STAYS PENDING
"IRET" N
RESTORE PC, X, A, CC FROM STACK
EXECUTE INSTRUCTION
STACK PC, X, A, CC LOAD I1:0 FROM INTERRUPT SW REG. LOAD PC FROM INTERRUPT VECTOR
Servicing pending interrupts
As several interrupts can be pending at the same time, the interrupt to be taken into account is determined by the following two-step process:

the highest software priority interrupt is serviced, if several interrupts have the same software priority then the interrupt with the highest hardware priority is serviced first.
Figure 18 describes this decision process. Figure 18. Priority decision process flowchart
PENDING INTERRUPTS
Same
SOFTWARE PRIORITY
Different
HIGHEST SOFTWARE PRIORITY SERVICED HIGHEST HARDWARE PRIORITY SERVICED
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Interrupts
When an interrupt request is not serviced immediately, it is latched and then processed when its software priority combined with the hardware priority becomes the highest one. Note: 1 2 The hardware priority is exclusive while the software one is not. This allows the previous process to succeed with only one interrupt. TLI, RESET and TRAP can be considered as having the highest software priority in the decision process.
Different interrupt vector sources
Two interrupt source types are managed by the ST7 interrupt controller: the non-maskable type (RESET, TRAP) and the maskable type (external or from internal peripherals).
Non-maskable sources
These sources are processed regardless of the state of the I1 and I0 bits of the CC register (see Figure 17). After stacking the PC, X, A and CC registers (except for RESET), the corresponding vector is loaded in the PC register and the I1 and I0 bits of the CC are set to disable interrupts (level 3). These sources allow the processor to exit Halt mode.
TRAP (non-maskable software interrupt) This software interrupt is serviced when the TRAP instruction is executed. It will be serviced according to the flowchart in Figure 17.
Caution:
TRAP can be interrupted by a TLI.
RESET The RESET source has the highest priority in the ST7. This means that the first current routine has the highest software priority (level 3) and the highest hardware priority. See Section 6.5: Reset sequence manager (RSM) for more details.
Maskable sources
Maskable interrupt vector sources can be serviced if the corresponding interrupt is enabled and if its own interrupt software priority (in ISPRx registers) is higher than the one currently being serviced (I1 and I0 in CC register). If any of these two conditions is false, the interrupt is latched and thus remains pending.
TLI (top level hardware interrupt)
Caution:
This hardware interrupt occurs when a specific edge is detected on the dedicated TLI pin. It will be serviced according to the flowchart in Figure 17 as a trap. A TRAP instruction must not be used in a TLI service routine.
External Interrupts External interrupts allow the processor to exit from HALT low power mode. External interrupt sensitivity is software selectable through the External Interrupt Control register (EICR). External interrupt triggered on edge will be latched and the interrupt request automatically cleared upon entering the interrupt service routine. If several input pins of a group connected to the same interrupt line are selected simultaneously, these will be logically ORed.
Peripheral Interrupts Usually the peripheral interrupts cause the MCU to exit from Halt mode except those mentioned in Table 19: Interrupt mapping. A peripheral interrupt occurs when a specific
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Interrupts
ST72321Bxxx-Auto flag is set in the peripheral status registers and if the corresponding enable bit is set in the peripheral control register. The general sequence for clearing an interrupt is based on an access to the status register followed by a read or write to an associated register.
Note:
The clearing sequence resets the internal latch. A pending interrupt (that is, waiting to be serviced) will therefore be lost if the clear sequence is executed.
7.3
Interrupts and low power modes
All interrupts allow the processor to exit the Wait low power mode. On the contrary, only external and other specified interrupts allow the processor to exit from the Halt modes (see column "Exit from Halt/Active Halt" in Table 19: Interrupt mapping). When several pending interrupts are present while exiting Halt mode, the first one serviced can only be an interrupt with "exit from Halt mode" capability and it is selected through the same decision process shown in Figure 18.
Note:
If an interrupt that is not able to exit from Halt mode is pending with the highest priority when exiting Halt mode, this interrupt is serviced after the first one serviced.
7.4
Concurrent and nested management
The following Figure 19 and Figure 20 show two different interrupt management modes. The first is called concurrent mode and does not allow an interrupt to be interrupted, unlike the nested mode in Figure 20. The interrupt hardware priority is given in this order from the lowest to the highest: MAIN, IT4, IT3, IT2, IT1, IT0, TLI. The software priority is given for each interrupt.
Warning:
A stack overflow may occur without notifying the software of the failure.
Figure 19. Concurrent interrupt management
SOFTWARE PRIORITY LEVEL 3 IT0 IT1 IT2 IT3 RIM IT4 MAIN 11 / 10 10 MAIN 3 3/0 11 IT1 3 3 3 3 TRAP
IT2
IT1
IT4
IT3
HARDWARE PRIORITY
TRAP
IT0
I1
I0
11 11 11 11 11 USED STACK = 10 BYTES
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ST72321Bxxx-Auto Figure 20. Nested interrupt management
Interrupts
SOFTWARE PRIORITY LEVEL 3 IT0 3 IT1 IT2 IT3 2 1 3 3 MAIN 10 3/0
TRAP
IT2
IT1
IT4
IT3
TRAP
IT0
I1
I0
11 11 00 01 11 11 USED STACK = 20 BYTES
HARDWARE PRIORITY
IT1 IT2
RIM IT4 MAIN 11 / 10 IT4
7.5
7.5.1
Interrupt register description
CPU CC register interrupt bits
CPU CC 7 1 6 1 5 I1 RW 4 H RW 3 I0 RW 2 N RW Reset value: 111x 1010 (xAh) 1 Z RW 0 C RW
Table 15.
Bit 5 3
CPU CC register interrupt bits description
Name I1 I0 Function
Interrupt Software Priority 1 Interrupt Software Priority 0
These two bits indicate the current interrupt software priority (see Table 16) and are set/cleared by hardware when entering in interrupt. The loaded value is given by the corresponding bits in the interrupt software priority registers (ISPRx). They can be also set/cleared by software with the RIM, SIM, HALT, WFI, IRET and PUSH/POP instructions (see Table 18: Interrupt dedicated instruction set).
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Interrupts Table 16. Interrupt software priority levels
Interrupt software priority Level 0 (main) Level 1 Level 2 Level 3 (= interrupt disable(1))
1. TLI, TRAP and RESET events can interrupt a level 3 program.
ST72321Bxxx-Auto
Level Low
I1 1 0 0
I0 0 1 0 1
High
1
7.5.2
Interrupt software priority registers (ISPRx)
These four registers are read/write, with the exception of bits 7:4 of ISPR3, which are read only.
ISPRx 7 ISPR0 ISPR1 ISPR2 ISPR3 I1_3 I1_7 I1_11 1 6 I0_3 I0_7 I0_11 1 5 I1_2 I1_6 I1_10 1 4 I0_2 I0_6 I0_10 1 3 I1_1 I1_5 I1_9 I1_13 Reset value: 1111 1111 (FFh) 2 I0_1 I0_5 I0_9 I0_13 1 I1_0 I1_4 I1_8 I1_12 0 I0_0 I0_4 I0_8 I0_12
These four registers contain the interrupt software priority of each interrupt vector.
Each interrupt vector (except RESET and TRAP) has corresponding bits in these registers where its own software priority is stored. This correspondence is shown in the following Table 17. Interrupt priority bits
Vector address FFFBh-FFFAh FFF9h-FFF8h ... FFE1h-FFE0h ISPRx bits I1_0 and I0_0 bits(1) I1_1 and I0_1 bits ... I1_13 and I0_13 bits
Table 17.
1. Bits in the ISPRx registers which correspond to the TLI can be read and written but they are not significant in the interrupt process management.
Each I1_x and I0_x bit value in the ISPRx registers has the same meaning as the I1 and I0 bits in the CC register. Level 0 cannot be written (I1_x = 1, I0_x = 0). In this case, the previously stored value is kept (Example: previous = CFh, write = 64h, result = 44h).
The TLI, RESET, and TRAP vectors have no software priorities. When one is serviced, the I1 and I0 bits of the CC register are both set. Caution: If the I1_x and I0_x bits are modified while the interrupt x is executed the following behavior has to be considered: If the interrupt x is still pending (new interrupt or flag not cleared) and the new software priority is higher than the previous one, the interrupt x is re-entered.
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Interrupts
Otherwise, the software priority stays unchanged up to the next interrupt request (after the IRET of the interrupt x). Table 18.
Instruction HALT IRET JRM JRNM POP CC RIM SIM TRAP WFI
Interrupt dedicated instruction set
New description Entering Halt mode Interrupt routine return Jump if I1:0 = 11 (level 3) Jump if I1:0 <> 11 Pop CC from the Stack Enable interrupt (level 0 set) Pop CC, A, X, PC I1:0 = 11 ? I1:0 <> 11 ? Mem => CC Load 10 in I1:0 of CC I1 1 1 1 1 H I0 0 1 1 0 N Z C Function/Example I1 1 I1 H H I0 0 I0 N Z C N Z C
Disable interrupt (level 3 set) Load 11 in I1:0 of CC Software trap Wait for interrupt Software NMI
Note:
During the execution of an interrupt routine, the HALT, POPCC, RIM, SIM and WFI instructions change the current software priority up to the next IRET instruction or one of the previously mentioned instructions.
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Interrupts Table 19. Interrupt mapping
ST72321Bxxx-Auto
No.
Source block
Description
Register label
Priority order
Exit from Halt / Active Halt yes
Address vector
RESET TRAP 0 1 2 3 4 5 6 7 8 9 10 11 12 13 SPI TIMER A TIMER B SCI AVD I2C PWM ART TLI
Reset N/A Software interrupt External top level interrupt EICR MCCSR Higher priority
FFFEh-FFFFh FFFCh-FFFDh FFFAh-FFFBh FFF8h-FFF9h FFF6h-FFF7h FFF4h-FFF5h FFF2h-FFF3h FFF0h-FFF1h FFEEh-FFEFh
no yes yes yes yes N/A yes yes
MCC/RTC Main clock controller time base interrupt ei0 ei1 ei2 ei3 External interrupt port A3..0 External interrupt port F2..0 External interrupt port B3..0 External interrupt port B7..4 Not used SPI peripheral interrupts TIMER A peripheral interrupts TIMER B peripheral interrupts SCI peripheral interrupts Auxiliary voltage detector interrupt I2C peripheral interrupts PWM ART interrupt
SPICSR TASR TBSR SCISR SICSR (see peripheral) ARTCSR Lower priority
yes
(1)
FFECh-FFEDh FFEAh-FFEBh FFE8h-FFE9h FFE6h-FFE7h FFE4h-FFE5h FFE2h-FFE3h FFE0h-FFE1h
no no no no no yes(2)
1. Exit from HALT possible when SPI is in slave mode. 2. Exit from HALT possible when PWM ART is in external clock mode.
7.6
7.6.1
External interrupts
I/O port interrupt sensitivity
The external interrupt sensitivity is controlled by the IPA, IPB and ISxx bits of the EICR register (Figure 21). This control allows to have up to four fully independent external interrupt source sensitivities. Each external interrupt source can be generated on four (or five) different events on the pin:

Falling edge Rising edge Falling and rising edge Falling edge and low level Rising edge and high level (only for ei0 and ei2)
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Interrupts
To guarantee correct functionality, the sensitivity bits in the EICR register can be modified only when the I1 and I0 bits of the CC register are both set to 1 (level 3). This means that interrupts must be disabled before changing sensitivity. The pending interrupts are cleared by writing a different value in the ISx[1:0], IPA or IPB bits of the EICR. Figure 21. External interrupt control bits
PORT A [3:0] INTERRUPTS PAOR.3 PADDR.3 PA3 CONTROL IPA BIT EICR IS20 IS21 PA3 PA2 PA1 PA0
SENSITIVITY
ei0 INTERRUPT SOURCE
PORT F [2:0] INTERRUPTS PFOR.2 PFDDR.2 PF2
EICR IS20 IS21 PF2 PF1 PF0
SENSITIVITY CONTROL
ei1 INTERRUPT SOURCE
PORT B [3:0] INTERRUPTS PBOR.3 PBDDR.3 PB3
EICR IS10 IS11 PB3 PB2 PB1 PB0
SENSITIVITY CONTROL
ei2 INTERRUPT SOURCE
IPB BIT
PORT B [7:4] INTERRUPTS PBOR.7 PBDDR.7 PB7
EICR IS10 IS11 PB7 PB6 PB5 PB4
SENSITIVITY CONTROL
ei3 INTERRUPT SOURCE
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Interrupts
ST72321Bxxx-Auto
7.6.2
External interrupt control register (EICR)
EICR 7 IS1[1:0] RW 6 5 IPB RW 4 IS2[1:0] RW 3 2 IPA RW Reset value: 0000 0000 (00h) 1 TLIS RW 0 TLIE RW
Table 20.
Bit Name
EICR register description
Function ei2 and ei3 sensitivity The interrupt sensitivity, defined using the IS1[1:0] bits, is applied to the following external interrupts: - ei2 (port B3..0) (see Table 21) - ei3 (port B7..4) (see Table 22) These 2 bits can be written only when I1 and I0 of the CC register are both set to 1 (level 3). Interrupt polarity for port B This bit is used to invert the sensitivity of the port B [3:0] external interrupts. It can be set and cleared by software only when I1 and I0 of the CC register are both set to 1 (level 3). 0: No sensitivity inversion 1: Sensitivity inversion ei0 and ei1 sensitivity The interrupt sensitivity, defined using the IS2[1:0] bits, is applied to the following external interrupts: - ei0 (port A3..0) (see Table 23) - ei1 (port F2..0) (see Table 24) These 2 bits can be written only when I1 and I0 of the CC register are both set to 1 (level 3). Interrupt polarity for port A This bit is used to invert the sensitivity of the port A [3:0] external interrupts. It can be set and cleared by software only when I1 and I0 of the CC register are both set to 1 (level 3). 0: No sensitivity inversion 1: Sensitivity inversion TLI sensitivity This bit allows to toggle the TLI edge sensitivity. It can be set and cleared by software only when TLIE bit is cleared. 0: Falling edge 1: Rising edge TLI enable This bit allows to enable or disable the TLI capability on the dedicated pin. It is set and cleared by software. 0: TLI disabled 1: TLI enabled Note: A parasitic interrupt can be generated when clearing the TLIE bit.
7:6
IS1[1:0]
5
IPB
4:3
IS2[1:0]
2
IPA
1
TLIS
0
TLIE
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ST72321Bxxx-Auto Table 21.
IS11 0 0 1 1
Interrupts Interrupt sensitivity - ei2 (port B3..0)
External interrupt sensitivity IS10 IPB bit = 0 0 1 0 1 Falling edge and low level Rising edge only Falling edge only Rising and falling edge IPB bit = 1 Rising edge and high level Falling edge only Rising edge only
Table 22.
IS11 0 0 1 1
Interrupt sensitivity - ei3 (port B7..4)
IS10 0 1 0 1 External interrupt sensitivity Falling edge and low level Rising edge only Falling edge only Rising and falling edge
Table 23.
IS21 0 0 1 1
Interrupt sensitivity - ei0 (port A3..0)
External interrupt sensitivity IS20 IPA bit = 0 0 1 0 1 Falling edge and low level Rising edge only Falling edge only Rising and falling edge IPA bit = 1 Rising edge and high level Falling edge only Rising edge only
Table 24.
IS21 0 0 1 1
Interrupt sensitivity - ei1 (port F2..0)
IS20 0 1 0 1 External interrupt sensitivity Falling edge and low level Rising edge only Falling edge only Rising and falling edge
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Interrupts Table 25. Nested interrupts register map and reset values
Register label 7 ei1 0024h ISPR0 Reset value I1_3 1 SPI 0025h ISPR1 Reset value I1_7 1 AVD 0026h ISPR2 Reset value I1_11 1 I0_11 1 I1_10 1 I0_7 1 I1_6 1 SCI I0_10 1 I0_6 1 I1_5 1 I0_3 1 I1_2 1 6 5 ei0 I0_2 1 I1_1 1 ei3 I0_5 1 4 3 MCC I0_1 1 2
ST72321Bxxx-Auto
Address (Hex.)
1 TLI 1 ei2 I1_4 1
0
1
I0_4 1
TIMER B I1_9 1 I0_9 1
TIMER A I1_8 1 I2C I1_12 1 TLIS 0 I0_12 1 TLIE 0 I0_8 1
PWMART 0027h ISPR3 Reset value EICR Reset value 1 IS11 0 1 IS10 0 1 IPB 0 1 IS21 0 I1_13 1 IS20 0 I0_13 1 IPA 0
0028h
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Power saving modes
8
8.1
Power saving modes
Introduction
To give a large measure of flexibility to the application in terms of power consumption, four main power saving modes are implemented in the ST7 (see Figure 22): Slow, Wait (Slow Wait), Active Halt and Halt. After a RESET the normal operating mode is selected by default (Run mode). This mode drives the device (CPU and embedded peripherals) by means of a master clock which is based on the main oscillator frequency divided or multiplied by 2 (fOSC2). From Run mode, the different power saving modes may be selected by setting the relevant register bits or by calling the specific ST7 software instruction whose action depends on the oscillator status. Figure 22. Power saving mode transitions
High RUN SLOW WAIT SLOW WAIT ACTIVE HALT HALT Low POWER CONSUMPTION
8.2
Slow mode
This mode has two targets:

To reduce power consumption by decreasing the internal clock in the device, To adapt the internal clock frequency (fCPU) to the available supply voltage.
Slow mode is controlled by three bits in the MCCSR register: the SMS bit which enables or disables Slow mode and two CPx bits which select the internal slow frequency (fCPU). In this mode, the master clock frequency (fOSC2) can be divided by 2, 4, 8 or 16. The CPU and peripherals are clocked at this lower frequency (fCPU). Note: Slow Wait mode is activated when entering the Wait mode while the device is already in Slow mode.
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Power saving modes Figure 23. Slow mode clock transitions
fOSC2/2 fCPU fOSC2/4
ST72321Bxxx-Auto
fOSC2
fOSC2 CP1:0 SMS 00 01
MCCSR
NORMAL RUN MODE NEW SLOW FREQUENCY REQUEST REQUEST
8.3
Wait mode
Wait mode places the MCU in a low power consumption mode by stopping the CPU. This power saving mode is selected by calling the `WFI' instruction. All peripherals remain active. During Wait mode, the I[1:0] bits of the CC register are forced to `10', to enable all interrupts. All other registers and memory remain unchanged. The MCU remains in Wait mode until an interrupt or RESET occurs, whereupon the Program Counter branches to the starting address of the interrupt or Reset service routine. The MCU will remain in Wait mode until a Reset or an Interrupt occurs, causing it to wake up. Refer to the following Figure 24.
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ST72321Bxxx-Auto Figure 24. Wait mode flowchart
Power saving modes
WFI INSTRUCTION
OSCILLATOR PERIPHERALS CPU I[1:0] BITS
ON ON OFF 10
N RESET N INTERRUPT Y OSCILLATOR PERIPHERALS CPU I[1:0] BITS ON OFF ON 10 Y
256 OR 4096 CPU CLOCK CYCLE DELAY
OSCILLATOR PERIPHERALS CPU I[1:0] BITS
ON ON ON XX(1)
FETCH RESET VECTOR OR SERVICE INTERRUPT
1. Before servicing an interrupt, the CC register is pushed on the stack. The I[1:0] bits of the CC register are set to the current software priority level of the interrupt routine and recovered when the CC register is popped.
8.4
Active Halt and Halt modes
Active Halt and Halt modes are the two lowest power consumption modes of the MCU. They are both entered by executing the `HALT' instruction. The decision to enter either in Active Halt or Halt mode is given by the MCC/RTC interrupt enable flag (OIE bit in MCCSR register) as shown in Table 26.
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Power saving modes Table 26. MCC/RTC low power mode selection
ST72321Bxxx-Auto
MCCSR OIE bit 0 1
Power saving mode entered when HALT instruction is executed Halt Active Halt
8.4.1
Active Halt mode
Active Halt mode is the lowest power consumption mode of the MCU with a real-time clock available. It is entered by executing the `HALT' instruction when the OIE bit of the Main Clock Controller Status register (MCCSR) is set (see Section 12.3: ART registers for more details on the MCCSR register). The MCU can exit Active Halt mode on reception of an external interrupt, MCC/RTC interrupt or a RESET. When exiting Active Halt mode by means of an interrupt, no 256 or 4096 CPU cycle delay occurs. The CPU resumes operation by servicing the interrupt or by fetching the reset vector which woke it up (see Figure 26). When entering Active Halt mode, the I[1:0] bits in the CC register are forced to `10b' to enable interrupts. Therefore, if an interrupt is pending, the MCU wakes up immediately. In Active Halt mode, only the main oscillator and its associated counter (MCC/RTC) are running to keep a wake-up time base. All other peripherals are not clocked except those which get their clock supply from another clock generator (such as external or auxiliary oscillator). The safeguard against staying locked in Active Halt mode is provided by the oscillator interrupt.
Note:
As soon as the interrupt capability of one of the oscillators is selected (MCCSR.OIE bit set), entering Active Halt mode while the Watchdog is active does not generate a RESET. This means that the device cannot spend more than a defined delay in this power saving mode.
Caution:
When exiting Active Halt mode following an MCC/RTC interrupt, OIE bit of MCCSR register must not be cleared before tDELAY after the interrupt occurs (tDELAY = 256 or 4096 tCPU delay depending on option byte). Otherwise, the ST7 enters Halt mode for the remaining tDELAY period. Figure 25. Active Halt timing overview
RUN
ACTIVE HALT
256 OR 4096 CPU CYCLE DELAY(1) RESET OR INTERRUPT
RUN
HALT INSTRUCTION [MCCSR.OIE = 1]
FETCH VECTOR
1. This delay occurs only if the MCU exits Active Halt mode by means of a RESET.
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ST72321Bxxx-Auto Figure 26. Active Halt mode flowchart
OSCILLATOR PERIPHERALS(1) CPU I[1:0] BITS N N
INTERRUPT
Power saving modes
HALT INSTRUCTION (MCCSR.OIE = 1)
ON OFF OFF 10
RESET Y
Y
OSCILLATOR PERIPHERALS CPU I[1:0] BITS
ON OFF ON XX(2)
256 OR 4096 CPU CLOCK CYCLE DELAY OSCILLATOR PERIPHERALS CPU I[1:0] BITS ON ON ON XX(2)
FETCH RESET VECTOR OR SERVICE INTERRUPT
1. Peripheral clocked with an external clock source can still be active. 2. Before servicing an interrupt, the CC register is pushed on the stack. The I[1:0] bits of the CC register are set to the current software priority level of the interrupt routine and restored when the CC register is popped.
8.4.2
Halt mode
The Halt mode is the lowest power consumption mode of the MCU. It is entered by executing the `HALT' instruction when the OIE bit of the Main Clock Controller Status register (MCCSR) is cleared (see Chapter 11: Main clock controller with real-time clock and beeper (MCC/RTC) for more details on the MCCSR register). The MCU can exit Halt mode on reception of either a specific interrupt (see Table 19: Interrupt mapping on page 62) or a RESET. When exiting Halt mode by means of a RESET or an interrupt, the oscillator is immediately turned on and the 256 or 4096 CPU cycle delay is used to stabilize the oscillator. After the start up delay, the CPU resumes operation by servicing the interrupt or by fetching the reset vector which woke it up (see Figure 28). When entering Halt mode, the I[1:0] bits in the CC register are forced to `10b' to enable interrupts. Therefore, if an interrupt is pending, the MCU wakes up immediately. In Halt mode, the main oscillator is turned off causing all internal processing to be stopped, including the operation of the on-chip peripherals. All peripherals are not clocked except the
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Power saving modes
ST72321Bxxx-Auto
ones which get their clock supply from another clock generator (such as an external or auxiliary oscillator). The compatibility of Watchdog operation with Halt mode is configured by the `WDGHALT' option bit of the option byte. The HALT instruction when executed while the Watchdog system is enabled, can generate a Watchdog RESET (see Section 21.1.1: Flash configuration on page 228 for more details). Figure 27. Halt timing overview
RUN
HALT
256 OR 4096 CPU CYCLE DELAY RESET OR INTERRUPT
RUN
HALT INSTRUCTION [MCCSR.OIE = 0]
FETCH VECTOR
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ST72321Bxxx-Auto Figure 28. Halt mode flowchart
HALT INSTRUCTION (MCCSR.OIE = 0) ENABLE WATCHDOG
Power saving modes
WDGHALT (1) 1 WATCHDOG RESET
0
DISABLE
OSCILLATOR PERIPHERALS (2) CPU I[1:0] BITS
OFF OFF OFF 10
N RESET N INTERRUPT (3) Y OSCILLATOR PERIPHERALS CPU I[1:0] BITS ON OFF ON XX (4) Y
256 OR 4096 CPU CLOCK CYCLE DELAY
OSCILLATOR PERIPHERALS CPU I[1:0] BITS
ON ON ON XX (4)
FETCH RESET VECTOR OR SERVICE INTERRUPT
1. WDGHALT is an option bit. See Section 21.1.1: Flash configuration for more details. 2. Peripheral clocked with an external clock source can still be active. 3. Only some specific interrupts can exit the MCU from Halt mode (such as external interrupt). Refer to Table 19: Interrupt mapping for more details. 4. Before servicing an interrupt, the CC register is pushed on the stack. The I[1:0] bits of the CC register are set to the current software priority level of the interrupt routine and recovered when the CC register is popped.
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Power saving modes
ST72321Bxxx-Auto
Halt mode recommendations

Make sure that an external event is available to wake up the microcontroller from Halt mode. When using an external interrupt to wake up the microcontroller, re-initialize the corresponding I/O as "Input Pull-up with Interrupt" before executing the HALT instruction. The main reason for this is that the I/O may be wrongly configured due to external interference or by an unforeseen logical condition. For the same reason, reinitialize the level sensitiveness of each external interrupt as a precautionary measure. The opcode for the HALT instruction is 0x8E. To avoid an unexpected HALT instruction due to a program counter failure, it is advised to clear all occurrences of the data value 0x8E from memory. For example, avoid defining a constant in ROM with the value 0x8E. As the HALT instruction clears the interrupt mask in the CC register to allow interrupts, the user may choose to clear all pending interrupt bits before executing the HALT instruction. This avoids entering other peripheral interrupt routines after executing the external interrupt routine corresponding to the wake-up event (reset or external interrupt).

Related documentation
ST7 Keypad Decoding Techniques, Implementing Wake-Up on Keystroke (AN 980) How to Minimize the ST7 Power Consumption (AN1014) Using an active RC to wake up the ST7LITE0 from power saving mode (AN1605)
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ST72321Bxxx-Auto
I/O ports
9
9.1
I/O ports
Introduction
The I/O ports offer different functional modes:
transfer of data through digital inputs and outputs external interrupt generation alternate signal input/output for the on-chip peripherals.
and for specific pins:

An I/O port contains up to eight pins. Each pin can be programmed independently as digital input (with or without interrupt generation) or digital output.
9.2
Functional description
Each port has two main registers:

Data Register (DR) Data Direction Register (DDR) Option Register (OR)
and one optional register:
Each I/O pin may be programmed using the corresponding register bits in the DDR and OR registers (bit X corresponding to pin X of the port). The same correspondence is used for the DR register. The following description takes into account the OR register (for specific ports which do not provide this register refer to Section 9.3: I/O port implementation on page 79). The generic I/O block diagram is shown in Figure 29.
9.2.1
Input modes
The input configuration is selected by clearing the corresponding DDR register bit. In this case, reading the DR register returns the digital value applied to the external I/O pin. Different input modes can be selected by software through the OR register.
Note:
1 2 3
Writing the DR register modifies the latch value but does not affect the pin status. When switching from input to output mode, the DR register has to be written first to drive the correct level on the pin as soon as the port is configured as an output. Do not use read/modify/write instructions (BSET or BRES) to modify the DR register as this might corrupt the DR content for I/Os configured as input.
External interrupt function
When an I/O is configured as Input with Interrupt, an event on this I/O can generate an external interrupt request to the CPU. Each pin can independently generate an interrupt request. The interrupt sensitivity is independently programmable using the sensitivity bits in the EICR register.
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I/O ports
ST72321Bxxx-Auto Each external interrupt vector is linked to a dedicated group of I/O port pins (see pinout description and interrupt section). If several input pins are selected simultaneously as interrupt sources, these are first detected according to the sensitivity bits in the EICR register and then logically ORed. The external interrupts are hardware interrupts, which means that the request latch (not accessible directly by the application) is automatically cleared when the corresponding interrupt vector is fetched. To clear an unwanted pending interrupt by software, the sensitivity bits in the EICR register must be modified.
9.2.2
Output modes
The output configuration is selected by setting the corresponding DDR register bit. In this case, writing the DR register applies this digital value to the I/O pin through the latch. Then reading the DR register returns the previously stored value. Two different output modes can be selected by software through the OR register: Output push-pull and open-drain. The DR register value and output pin status are shown in the following Table 27. Table 27. I/O output mode selection
DR 0 1 Push-pull VSS VDD Open-drain VSS Floating
9.2.3
Alternate functions
When an on-chip peripheral is configured to use a pin, the alternate function is automatically selected. This alternate function takes priority over the standard I/O programming. When the signal is coming from an on-chip peripheral, the I/O pin is automatically configured in output mode (push-pull or open-drain according to the peripheral). When the signal is going to an on-chip peripheral, the I/O pin must be configured in input mode. In this case, the pin state is also digitally readable by addressing the DR register.
Note:
Input pull-up configuration can cause unexpected value at the input of the alternate peripheral input. When an on-chip peripheral use a pin as input and output, this pin has to be configured in input floating mode.
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ST72321Bxxx-Auto Figure 29. I/O port general block diagram
REGISTER ACCESS ALTERNATE OUTPUT 1 0 ALTERNATE ENABLE DR
I/O ports
VDD
P-BUFFER (see table below) PULL-UP (see table below) VDD
DDR PULL-UP CONDITION If implemented OR SEL N-BUFFER DDR SEL CMOS SCHMITT TRIGGER ANALOG INPUT DIODES (see table below) PAD
OR
EXTERNAL INTERRUPT SOURCE (eix)
Table 28.
Input Pull-up with/without Interrupt Push-pull Off Output Open-drain (logic level) True open-drain NI On
1. The diode to VDD is not implemented in the true open-drain pads. A local protection between the pad and VSS is implemented to protect the device against positive stress.
Legend: Off - Implemented not activated On - Implemented and activated NI - Not implemented
DATA BUS
DR SEL
1 0
ALTERNATE INPUT
I/O port mode options
Diodes Configuration mode Floating with/without Interrupt Pull-up Off Off On On Off NI NI(1) On P-buffer to VDD to VSS
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I/O ports Table 29. I/O port configurations
Hardware configuration
ST72321Bxxx-Auto
NOT IMPLEMENTED IN TRUE OPEN DRAIN I/O PORTS
VDD RPU PULL-UP CONDITION
DR REGISTER ACCESS
DR REGISTER
W DATA BUS R
PAD
Input(1)
ALTERNATE INPUT
EXTERNAL INTERRUPT SOURCE (eix) INTERRUPT CONDITION ANALOG INPUT
Open-drain output(2)
NOT IMPLEMENTED IN TRUE OPEN DRAIN I/O PORTS
DR REGISTER ACCESS VDD RPU
PAD
DR REGISTER
R/W DATA BUS
ALTERNATE ENABLE
ALTERNATE OUTPUT
Push-pull output(2)
NOT IMPLEMENTED IN TRUE OPEN DRAIN I/O PORTS
DR REGISTER ACCESS VDD RPU
PAD
DR REGISTER
R/W DATA BUS
ALTERNATE ENABLE
ALTERNATE OUTPUT
1. When the I/O port is in input configuration and the associated alternate function is enabled as an output, reading the DR register will read the alternate function output status. 2. When the I/O port is in output configuration and the associated alternate function is enabled as an input, the alternate function reads the pin status given by the DR register content.
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ST72321Bxxx-Auto Caution:
I/O ports
The alternate function must not be activated as long as the pin is configured as input with interrupt, in order to avoid generating spurious interrupts.
Analog alternate function
When the pin is used as an ADC input, the I/O must be configured as floating input. The analog multiplexer (controlled by the ADC registers) switches the analog voltage present on the selected pin to the common analog rail which is connected to the ADC input. It is recommended not to change the voltage level or loading on any port pin while conversion is in progress. Furthermore it is recommended not to have clocking pins located close to a selected analog pin.
Warning:
The analog input voltage level must be within the limits stated in the absolute maximum ratings.
9.3
I/O port implementation
The hardware implementation on each I/O port depends on the settings in the DDR and OR registers and specific feature of the I/O port such as ADC Input or true open-drain. Switching these I/O ports from one state to another should be done in a sequence that prevents unwanted side effects. Recommended safe transitions are illustrated in Figure 30. Other transitions are potentially risky and should be avoided, since they are likely to present unwanted side-effects such as spurious interrupt generation. Figure 30. Interrupt I/O port state transitions
01 INPUT floating/pull-up interrupt
00 INPUT floating (reset state)
10 OUTPUT open-drain
11 OUTPUT push-pull
XX
= DDR, OR
The I/O port register configurations are summarized in the following table. Table 30.
Port
I/O port configuration
Input (DDR = 0) Pin name OR = 0 OR = 1 floating floating floating floating pull-up floating interrupt pull-up interrupt OR = 0 OR = 1 Output (DDR = 1)
PA7:6 PA5:4 Port A PA3 PA2:0
true open-drain open-drain open-drain open-drain push-pull push-pull push-pull
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I/O ports Table 30.
Port
ST72321Bxxx-Auto I/O port configuration (continued)
Input (DDR = 0) Pin name OR = 0 PB7, PB3 Port B PB6:5, PB4, PB2:0 Port C PC7:0 Port D PD7:0 PE7:3, PE1:0 Port E PE2 PF7:3 Port F PF2 PF1:0 floating floating floating pull-up pull-up floating interrupt pull-up interrupt floating floating floating floating pull-up interrupt pull-up pull-up pull-up open-drain open-drain open-drain open-drain open-drain
(1)
Output (DDR = 1) OR = 0 open-drain OR = 1 push-pull push-pull push-pull push-pull push-pull push-pull(1) push-pull push-pull push-pull
OR = 1 floating interrupt
floating
open-drain open-drain open-drain
1. Pull-up is always enabled leading to unwanted power consumption if output is tied to low level
9.4
Low power modes
Table 31.
Mode Wait Halt
Effect of low power modes on I/O ports
Effect No effect on I/O ports. External interrupts cause the device to exit from Wait mode. No effect on I/O ports. External interrupts cause the device to exit from Halt mode.
9.5
Interrupts
The external interrupt event generates an interrupt if the corresponding configuration is selected with DDR and OR registers and the interrupt mask in the CC register is not active (RIM instruction). Table 32. I/O port interrupt control/wake-up capability
Interrupt event External interrupt on selected external event Event flag Enable control bit DDRx, ORx Exit from Wait Yes Exit from Halt Yes
Table 33.
I/O port register map and reset values
Register label 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0
Address (Hex.)
Reset value of all I/O port registers 0000h 0001h 0002h PADR PADDR PAOR
MSB
LSB
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ST72321Bxxx-Auto Table 33. I/O port register map and reset values (continued)
Register label 7 0 6 0 5 0 4 0 3 0 2 0 1 0
I/O ports
Address (Hex.)
0 0
Reset value of all I/O port registers 0003h 0004h 0005h 0006h 0007h 0008h 0009h 000Ah 000Bh 000Ch 000Dh 000Eh 000Fh 0010h 0011h PBDR PBDDR PBOR PCDR PCDDR PCOR PDDR PDDDR PDOR PEDR PEDDR PEOR PFDR PFDDR PFOR
MSB
LSB
MSB
LSB
MSB
LSB
MSB
LSB
MSB
LSB
Related documentation
SPI Communication between ST7 and EEPROM (AN 970) S/W implementation of I2C bus master (AN1045) Software LCD driver (AN1048)
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Watchdog timer (WDG)
ST72321Bxxx-Auto
10
10.1
Watchdog timer (WDG)
Introduction
The Watchdog timer is used to detect the occurrence of a software fault, usually generated by external interference or by unforeseen logical conditions, which causes the application program to abandon its normal sequence. The Watchdog circuit generates an MCU reset on expiry of a programmed time period, unless the program refreshes the counter's contents before the T6 bit becomes cleared.
10.2
Main features

Programmable free-running downcounter Programmable reset Reset (if watchdog activated) when the T6 bit reaches zero Optional reset on HALT instruction (configurable by option byte) Hardware Watchdog selectable by option byte
10.3
Functional description
The counter value stored in the Watchdog Control register (WDGCR bits T[6:0]), is decremented every 16384 fOSC2 cycles (approx.), and the length of the timeout period can be programmed by the user in 64 increments. If the watchdog is activated (the WDGA bit is set) and when the 7-bit timer (bits T[6:0]) rolls over from 40h to 3Fh (T6 becomes cleared), it initiates a reset cycle pulling the RESET pin low for typically 30s. The application program must write in the WDGCR register at regular intervals during normal operation to prevent an MCU reset. This downcounter is free-running: It counts down even if the watchdog is disabled. The value to be stored in the WDGCR register must be between FFh and C0h: - - - The WDGA bit is set (watchdog enabled) The T6 bit is set to prevent generating an immediate reset The T[5:0] bits contain the number of increments which represents the time delay before the watchdog produces a reset (see Figure 32: Approximate timeout duration). The timing varies between a minimum and a maximum value due to the unknown status of the prescaler when writing to the WDGCR register (see Figure 33).
Following a reset, the watchdog is disabled. Once activated it cannot be disabled, except by a reset. The T6 bit can be used to generate a software reset (the WDGA bit is set and the T6 bit is cleared). If the watchdog is activated, the HALT instruction will generate a Reset.
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ST72321Bxxx-Auto Figure 31. Watchdog block diagram
RESET fOSC2
Watchdog timer (WDG)
MCC/RTC
WATCHDOG CONTROL REGISTER (WDGCR) DIV 64 WDGA T6 T5 T4 T3 T2 T1 T0
6-BIT DOWNCOUNTER (CNT)
12-BIT MCC RTC COUNTER MSB 11 65 LSB 0 TB[1:0] bits (MCCSR Register)
WDG PRESCALER DIV 4
10.4
How to program the watchdog timeout
Figure 32 shows the linear relationship between the 6-bit value to be loaded in the Watchdog Counter (CNT) and the resulting timeout duration in milliseconds. This can be used for a quick calculation without taking the timing variations into account. If more precision is needed, use the formulae in Figure 33.
Caution:
When writing to the WDGCR register, always write 1 in the T6 bit to avoid generating an immediate reset. Figure 32. Approximate timeout duration
3F 38 30
CNT Value (hex.)
28 20 18
10 08 00 1.5 18 34 50 65 82 98 114 128 Watchdog timeout (ms) @ 8 MHz fOSC2
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Watchdog timer (WDG) Figure 33. Exact timeout duration (tmin and tmax)
WHERE: tmin0 = (LSB + 128) x 64 x tOSC2 tmax0 = 16384 x tOSC2 tOSC2 = 125ns if fOSC2= 8 MHz
ST72321Bxxx-Auto
CNT = Value of T[5:0] bits in the WDGCR register (6 bits) MSB and LSB are values from the table below depending on the timebase selected by the TB[1:0] bits in the MCCSR register
TB1 bit (MCCSR reg.) 0 0 1 1 TB0 bit (MCCSR reg.) 0 1 0 1 Selected MCCSR timebase 2ms 4ms 10ms 25ms MSB 4 8 20 49 LSB 59 53 35 54
To calculate the minimum Watchdog Timeout (tmin): IF CNT < MSB ------------4
THEN tmin = t min0 + 16384 x CNT x tosc2 ELSE t min = tmin0 + 16384 x CNT - 4CNT + ( 192 + LSB ) x 64 x 4CNT ------------------------------ MSB MSB
x tosc2
To calculate the maximum Watchdog Timeout (tmax): IF CNT MSB ------------4
THEN t max = t max0 + 16384 x CNT x t osc2 ELSE t max = tmax0 + 16384 x CNT - 4CNT + ( 192 + LSB ) x 64 x 4CNT ------------------------------ MSB MSB
x t osc2
Note: In the above formulae, division results must be rounded down to the next integer value. Example: With 2ms timeout selected in MCCSR register
Value of T[5:0] bits in WDGCR register (Hex.) 00 3F Min. Watchdog Timeout (ms) tmin 1.496 128 Max. Watchdog Timeout (ms) tmax 2.048 128.552
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ST72321Bxxx-Auto
Watchdog timer (WDG)
10.5
Low power modes
Table 34.
Mode Slow Wait No effect on Watchdog No effect on Watchdog OIE bit in MCCSR register WDGHALT bit in Option Byte No Watchdog reset is generated. The MCU enters Halt mode. The Watchdog counter is decremented once and then stops counting and is no longer able to generate a watchdog reset until the MCU receives an external interrupt or a reset. If an external interrupt is received, the Watchdog restarts counting after 256 or 4096 CPU clocks. If a reset is generated, the Watchdog is disabled (reset state) unless Hardware Watchdog is selected by option byte. For application recommendations see Section 10.7 below. A reset is generated. No reset is generated. The MCU enters Active Halt mode. The Watchdog counter is not decremented. It stop counting. When the MCU receives an oscillator interrupt or external interrupt, the Watchdog restarts counting immediately. When the MCU receives a reset the Watchdog restarts counting after 256 or 4096 CPU clocks.
Effect of low power modes on WDG
Effect
0 Halt
0
0
1
1
x
10.6
Hardware watchdog option
If Hardware Watchdog is selected by option byte, the watchdog is always active and the WDGA bit in the WDGCR is not used. Refer to the option byte description in Section 21.1.1: Flash configuration on page 228.
10.7
Using Halt mode with the WDG (WDGHALT option)
The following recommendation applies if Halt mode is used when the watchdog is enabled: Before executing the HALT instruction, refresh the WDG counter to avoid an unexpected WDG reset immediately after waking up the microcontroller.
10.8
Interrupts
None.
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Watchdog timer (WDG)
ST72321Bxxx-Auto
10.9
10.9.1
Register description
Control register (WDGCR)
WDGCR 7 WDGA RW 6 5 4 3 T[6:0] RW 2 Reset value: 0111 1111 (7Fh) 1 0
Table 35.
Bit Name
WDGCR register description
Function
7
Activation bit This bit is set by software and only cleared by hardware after a reset. When WDGA = 1, the watchdog can generate a reset. WDGA 0: Watchdog disabled 1: Watchdog enabled Note: This bit is not used if the hardware watchdog option is enabled by option byte. 7-bit counter (MSB to LSB) These bits contain the value of the watchdog counter. It is decremented every 16384 T[6:0] fOSC2 cycles (approx.). A reset is produced when it rolls over from 40h to 3Fh (T6 becomes cleared).
6:0
Table 36.
Address (Hex.) 002Ah
Watchdog timer register map and reset values
Register label WDGCR Reset Value 7 WDGA 0 6 T6 1 5 T5 1 4 T4 1 3 T3 1 2 T2 1 1 T1 1 0 T0 1
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ST72321Bxxx-Auto
Main clock controller with real-time clock and beeper (MCC/RTC)
11
Main clock controller with real-time clock and beeper (MCC/RTC)
Introduction
The Main Clock Controller consists of three different functions:

11.1
a programmable CPU clock prescaler a clock-out signal to supply external devices a real-time clock timer with interrupt capability
Each function can be used independently and simultaneously.
11.2
Programmable CPU clock prescaler
The programmable CPU clock prescaler supplies the clock for the ST7 CPU and its internal peripherals. It manages Slow power saving mode (see Section 8.2: Slow mode on page 67 for more details). The prescaler selects the fCPU main clock frequency and is controlled by three bits in the MCCSR register: CP[1:0] and SMS.
11.3
Clock-out capability
The clock-out capability is an alternate function of an I/O port pin that outputs a fCPU clock to drive external devices. It is controlled by the MCO bit in the MCCSR register.
Caution:
When selected, the clock out pin suspends the clock during Active Halt mode.
11.4
Real-time clock timer (RTC)
The counter of the real-time clock timer allows an interrupt to be generated based on an accurate real-time clock. Four different time bases depending directly on fOSC2 are available. The whole functionality is controlled by four bits of the MCCSR register: TB[1:0], OIE and OIF. When the RTC interrupt is enabled (OIE bit set), the ST7 enters Active Halt mode when the HALT instruction is executed. See Section 8.4: Active Halt and Halt modes on page 69 for more details.
11.5
Beeper
The beep function is controlled by the MCCBCR register. It can output three selectable frequencies on the BEEP pin (I/O port alternate function).
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Main clock controller with real-time clock and beeper (MCC/RTC) Figure 34. Main clock controller (MCC/RTC) block diagram
ST72321Bxxx-Auto
BC1 MCCBCR
BC0
BEEP BEEP SIGNAL SELECTION MCO
DIV 64
12-BIT MCC RTC COUNTER
TO WATCHDOG TIMER
MCO MCCSR fOSC2
CP1
CP0
SMS
TB1
TB0
OIE
OIF MCC/RTC INTERRUPT
DIV 2, 4, 8, 16
1
fCPU
0
CPU CLOCK TO CPU AND PERIPHERALS
11.6
Low power modes
Table 37.
Mode Wait Active Halt
Effect of low power modes on MCC/RTC
Effect No effect on MCC/RTC peripheral. MCC/RTC interrupt causes the device to exit from Wait mode. No effect on MCC/RTC counter (OIE bit is set), the registers are frozen. MCC/RTC interrupt causes the device to exit from Active Halt mode. MCC/RTC counter and registers are frozen. MCC/RTC operation resumes when the MCU is woken up by an interrupt with "exit from HALT" capability.
Halt
11.7
Interrupts
The MCC/RTC interrupt event generates an interrupt if the OIE bit of the MCCSR register is set and the interrupt mask in the CC register is not active (RIM instruction). Table 38. MCC/RTC interrupt control/wake-up capability
Interrupt event Time base overflow event Event flag OIF Enable control bit OIE Exit from Wait Yes Exit from Halt No(1)
1. The MCC/RTC interrupt wakes up the MCU from Active Halt mode, not from Halt mode.
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ST72321Bxxx-Auto
Main clock controller with real-time clock and beeper (MCC/RTC)
11.8
11.8.1
Main clock controller registers
MCC control/status register (MCCSR)
MCCSR 7 MCO RW 6 CP[1:0] RW 5 4 SMS RW 3 TB[1:0] RW 2 Reset value: 0000 0000 (00h) 1 OIE RW 0 OIF RW
Table 39.
Bit Name
MCCSR register description
Function Main clock out selection This bit enables the MCO alternate function on the PF0 I/O port. It is set and cleared by software. 0: MCO alternate function disabled (I/O pin free for general-purpose I/O) 1: MCO alternate function enabled (fCPU on I/O port) Note: To reduce power consumption, the MCO function is not active in Active Halt mode.
7
MCO
6:5
CPU clock prescaler These bits select the CPU clock prescaler which is applied in the different slow modes. Their action is conditioned by the setting of the SMS bit. These two bits are set and cleared by software. CP[1:0] 00: fCPU in Slow mode = fOSC2/2 01: fCPU in Slow mode = fOSC2/4 10: fCPU in Slow mode = fOSC2/8 11: fCPU in Slow mode = fOSC2/16 Slow mode select This bit is set and cleared by software. 0: Normal mode. fCPU = fOSC2 1: Slow mode. fCPU is given by CP1, CP0 See Section 8.2: Slow mode on page 67 and Chapter 11: Main clock controller with real-time clock and beeper (MCC/RTC) for more details.
4
SMS
3:2
Time base control These bits select the programmable divider time base. They are set and cleared by software (see Table 40). TB[1:0] A modification of the time base is taken into account at the end of the current period (previously set) to avoid an unwanted time shift. This allows to use this time base as a real-time clock. Oscillator interrupt enable This bit set and cleared by software. 0: Oscillator interrupt disabled 1: Oscillator interrupt enabled This interrupt can be used to exit from Active Halt mode. When this bit is set, calling the ST7 software HALT instruction enters the Active Halt power saving mode.
1
OIE
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Main clock controller with real-time clock and beeper (MCC/RTC) Table 39.
Bit Name
ST72321Bxxx-Auto
MCCSR register description (continued)
Function Oscillator interrupt flag This bit is set by hardware and cleared by software reading the MCCSR register. It indicates when set that the main oscillator has reached the selected elapsed time (TB1:0). 0: Timeout not reached 1: Timeout reached Caution: The BRES and BSET instructions must not be used on the MCCSR register to avoid unintentionally clearing the OIF bit.
0
OIF
Table 40.
Time base selection
Time base TB1 fOSC2 = 4 MHz fOSC2 = 8 MHz 2ms 4ms 10ms 25ms 0 0 1 1 0 1 0 1 4ms 8ms 20ms 50ms TB0
Counter prescaler 16000 32000 80000 200000
11.8.2
MCC beep control register (MCCBCR)
MCCBCR 7 6 5 Reserved 4 3 2 Reset value: 0000 0000 (00h) 1 BC[1:0] RW 0
Table 41.
Bit 7:2 1:0 Name -
MCCBCR register description
Function Reserved, must be kept cleared. Beep control These 2 bits select the PF1 pin beep capability (see Table 42).
BC[1:0]
Table 42.
BC1 0 0 1 1
Beep frequency selection
BC0 0 1 0 1 ~2 kHz ~1 kHz ~500 Hz Beep mode with fOSC2 = 8 MHz Off Output Beep signal ~50% duty cycle
The beep output signal is available in Active Halt mode but has to be disabled to reduce consumption.
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ST72321Bxxx-Auto Table 43.
Main clock controller with real-time clock and beeper (MCC/RTC)
Main clock controller register map and reset values
7 AVDS 0 MCO 0 0 6 AVDIE 0 CP1 0 0 5 AVDF 0 CP0 0 0 4 LVDRF x SMS 0 0 3 0 TB1 0 0 2 0 TB0 0 0 1 0 OIE 0 BC1 0 0 WDGRF x OIF 0 BC0 0
Address (Hex.) Register label 002Bh 002Ch 002Dh SICSR Reset value MCCSR Reset value MCCBCR Reset value
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PWM auto-reload timer (ART)
ST72321Bxxx-Auto
12
12.1
PWM auto-reload timer (ART)
Introduction
The Pulse Width Modulated Auto-Reload Timer on-chip peripheral consists of an 8-bit autoreload counter with compare/capture capabilities and of a 7-bit prescaler clock source. These resources allow five possible operating modes:

Generation of up to 4 independent PWM signals Output compare and Time base interrupt Up to 2 input capture functions External event detector Up to 2 external interrupt sources
The three first modes can be used together with a single counter frequency. The timer can be used to wake up the MCU from Wait and Halt modes. Figure 35. PWM auto-reload timer block diagram
PWMCR OEx OPx OCRx REGISTER LOAD PWMx PORT ALTERNATE FUNCTION POLARITY CONTROL COMPARE DCRx REGISTER
ARR REGISTER
8-BIT COUNTER (CAR REGISTER)
LOAD
ARTICx
INPUT CAPTURE CONTROL
LOAD
ICRx REGISTER
ICSx
ICIEx
ICFx
ICCSR ICx INTERRUPT
ARTCLK
fEXT fCPU fCOUNTER
MUX fINPUT
PROGRAMMABLE PRESCALER
EXCL
CC2
CC1
CC0
TCE
FCRL
OIE
OVF
ARTCSR OVF INTERRUPT
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ST72321Bxxx-Auto
PWM auto-reload timer (ART)
12.2
12.2.1
Functional description
Counter
The free running 8-bit counter is fed by the output of the prescaler, and is incremented on every rising edge of the clock signal. It is possible to read or write the contents of the counter on the fly by reading or writing the Counter Access register (ARTCAR). When a counter overflow occurs, the counter is automatically reloaded with the contents of the ARTARR register (the prescaler is not affected).
12.2.2
Counter clock and prescaler
The counter clock frequency is given by: fCOUNTER = fINPUT / 2CC[2:0] The timer counter's input clock (fINPUT) feeds the 7-bit programmable prescaler, which selects one of the 8 available taps of the prescaler, as defined by CC[2:0] bits in the Control/Status Register (ARTCSR). Thus the division factor of the prescaler can be set to 2n (where n = 0, 1,..7). This fINPUT frequency source is selected through the EXCL bit of the ARTCSR register and can be either the fCPU or an external input frequency fEXT. The clock input to the counter is enabled by the TCE (Timer Counter Enable) bit in the ARTCSR register. When TCE is reset, the counter is stopped and the prescaler and counter contents are frozen. When TCE is set, the counter runs at the rate of the selected clock source.
12.2.3
Counter and prescaler initialization
After RESET, the counter and the prescaler are cleared and fINPUT = fCPU. The counter can be initialized by:

writing to the ARTARR register and then setting the FCRL (Force Counter Re-Load) and the TCE (Timer Counter Enable) bits in the ARTCSR register writing to the ARTCAR counter access register
In both cases the 7-bit prescaler is also cleared, whereupon counting will start from a known value. Direct access to the prescaler is not possible.
12.2.4
Output compare control
The timer compare function is based on four different comparisons with the counter (one for each PWMx output). Each comparison is made between the counter value and an output compare register (OCRx) value. This OCRx register can not be accessed directly, it is loaded from the duty cycle register (PWMDCRx) at each overflow of the counter. This double buffering method avoids glitch generation when changing the duty cycle on the fly.
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PWM auto-reload timer (ART) Figure 36. Output compare control
fCOUNTER ARTARR = FDh COUNTER FDh FEh FFh FDh FEh FFh FDh
ST72321Bxxx-Auto
FEh
FFh
OCRx
FDh
FEh
PWMDCRx
FDh
FEh
PWMx
12.2.5
Independent PWM signal generation
This mode allows up to four Pulse Width Modulated signals to be generated on the PWMx output pins with minimum core processing overhead. This function is stopped during Halt mode. Each PWMx output signal can be selected independently using the corresponding OEx bit in the PWM Control register (PWMCR). When this bit is set, the corresponding I/O pin is configured as output push-pull alternate function. The PWM signals all have the same frequency which is controlled by the counter period and the ARTARR register value. fPWM = fCOUNTER / (256 - ARTARR) When a counter overflow occurs, the PWMx pin level is changed depending on the corresponding OPx (output polarity) bit in the PWMCR register. When the counter reaches the value contained in one of the output compare register (OCRx) the corresponding PWMx pin level is restored. It should be noted that the reload values will also affect the value and the resolution of the duty cycle of the PWM output signal. To obtain a signal on a PWMx pin, the contents of the OCRx register must be greater than the contents of the ARTARR register. The maximum available resolution for the PWMx duty cycle is: Resolution = 1 / (256 - ARTARR)
Note:
To get the maximum resolution (1/256), the ARTARR register must be 0. With this maximum resolution, 0% and 100% can be obtained by changing the polarity.
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ST72321Bxxx-Auto Figure 37. PWM auto-reload timer function
255 DUTY CYCLE REGISTER (PWMDCRx)
PWM auto-reload timer (ART)
COUNTER
AUTO-RELOAD REGISTER (ARTARR) 000 t
PWMx OUTPUT
WITH OEx=1 AND OPx=0 WITH OEx=1 AND OPx=1
Figure 38. PWM signal from 0% to 100% duty cycle
fCOUNTER ARTARR = FDh COUNTER FDh FEh FFh FDh FEh FFh FDh FEh
OCRx=FCh PWMx OUTPUT WITH OEx=1 AND OPx=0 OCRx=FDh OCRx=FEh OCRx=FFh t
12.2.6
Output compare and time base interrupt
On overflow, the OVF flag of the ARTCSR register is set and an overflow interrupt request is generated if the overflow interrupt enable bit, OIE, in the ARTCSR register, is set. The OVF flag must be reset by the user software. This interrupt can be used as a time base in the application.
12.2.7
External clock and event detector mode
Using the fEXT external prescaler input clock, the auto-reload timer can be used as an external clock event detector. In this mode, the ARTARR register is used to select the nEVENT number of events to be counted before setting the OVF flag. nEVENT = 256 - ARTARR
Caution:
The external clock function is not available in Halt mode. If Halt mode is used in the application, prior to executing the HALT instruction, the counter must be disabled by clearing the TCE bit in the ARTCSR register to avoid spurious counter increments.
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PWM auto-reload timer (ART) Figure 39. External event detector example (3 counts)
fEXT = fCOUNTER ARTARR = FDh
ST72321Bxxx-Auto
COUNTER
FDh
FEh
FFh
FDh
FEh
FFh
FDh
OVF
ARTCSR READ INTERRUPT IF OIE = 1 INTERRUPT IF OIE = 1
ARTCSR READ
t
12.2.8
Input capture function
This mode allows the measurement of external signal pulse widths through ARTICRx registers. Each input capture can generate an interrupt independently on a selected input signal transition. This event is flagged by a set of the corresponding CFx bits of the Input Capture Control/Status register (ARTICCSR). These input capture interrupts are enabled through the CIEx bits of the ARTICCSR register. The active transition (falling or rising edge) is software programmable through the CSx bits of the ARTICCSR register. The read only input capture registers (ARTICRx) are used to latch the auto-reload counter value when a transition is detected on the ARTICx pin (CFx bit set in ARTICCSR register). After fetching the interrupt vector, the CFx flags can be read to identify the interrupt source.
Note:
After a capture detection, data transfer in the ARTICRx register is inhibited until it is read (clearing the CFx bit). The timer interrupt remains pending while the CFx flag is set when the interrupt is enabled (CIEx bit set). This means that the ARTICRx register has to be read at each capture event to clear the CFx flag. The timing resolution is given by auto-reload counter cycle time (1/fCOUNTER).
Note:
During Halt mode, if both the input capture and the external clock are enabled, the ARTICRx register value is not guaranteed if the input capture pin and the external clock change simultaneously.
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ST72321Bxxx-Auto
PWM auto-reload timer (ART)
12.2.9
External interrupt capability
This mode allows the input capture capabilities to be used as external interrupt sources. The interrupts are generated on the edge of the ARTICx signal. The edge sensitivity of the external interrupts is programmable (CSx bit of ARTICCSR register) and they are independently enabled through CIEx bits of the ARTICCSR register. After fetching the interrupt vector, the CFx flags can be read to identify the interrupt source. During Halt mode, the external interrupts can be used to wake up the micro (if the CIEx bit is set). Figure 40. Input capture timing diagram
fCOUNTER
COUNTER
01h
02h
03h
04h
05h
06h
07h
ARTICx PIN CFx FLAG xxh ICRx REGISTER
INTERRUPT
04h t
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PWM auto-reload timer (ART)
ST72321Bxxx-Auto
12.3
12.3.1
ART registers
Control/status register (ARTCSR)
ARTCSR 7 EXCL RW 6 5 CC[2:0] RW 4 3 TCE RW 2 FCRL RW Reset value: 0000 0000 (00h) 1 OIE RW 0 OVF RW
Table 44.
Bit Name
ARTCSR register description
Function External Clock This bit is set and cleared by software. It selects the input clock for the 7-bit prescaler. 0: CPU clock 1: External clock Counter Clock Control These bits are set and cleared by software. They determine the prescaler division ratio from fINPUT (see Table 45). Timer Counter Enable This bit is set and cleared by software. It puts the timer in the lowest power consumption mode. 0: Counter stopped (prescaler and counter frozen) 1: Counter running Force Counter Re-Load This bit is write-only and any attempt to read it will yield a logical zero. When set, it causes the contents of ARTARR register to be loaded into the counter, and the content of the prescaler register to be cleared in order to initialize the timer before starting to count. Overflow Interrupt Enable This bit is set and cleared by software. It allows to enable/disable the interrupt which is generated when the OVF bit is set. 0: Overflow Interrupt disable 1: Overflow Interrupt enable Overflow Flag This bit is set by hardware and cleared by software reading the ARTCSR register. It indicates the transition of the counter from FFh to the ARTARR value. 0: New transition not yet reached 1: Transition reached
7
EXCL
6:4 CC[2:0]
3
TCE
2
FCRL
1
OIE
0
OVF
Table 45.
Prescaler selection for ART
With fINPUT = 8 MHz 8 MHz 4 MHz 2 MHz CC2 0 0 0 CC1 0 0 1 CC0 0 1 0
fCOUNTER fINPUT fINPUT / 2 fINPUT / 4
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ST72321Bxxx-Auto Table 45. Prescaler selection for ART (continued)
With fINPUT = 8 MHz 1 MHz 500 kHz 250 kHz 125 kHz 62.5 kHz
PWM auto-reload timer (ART)
fCOUNTER fINPUT / 8 fINPUT / 16 fINPUT / 32 fINPUT / 64 fINPUT / 128
CC2 0 1 1 1 1
CC1 1 0 0 1 1
CC0 1 0 1 0 1
12.3.2
Counter access register (ARTCAR)
ARTCAR 7 6 5 4 CA[7:0] RW 3 2 Reset value: 0000 0000 (00h) 1 0
Table 46.
Bit
ARTCAR register description
Function Counter Access Data These bits can be set and cleared either by hardware or by software. The ARTCAR register is used to read or write the auto-reload counter "on the fly" (while it is counting).
Name
7:0
CA[7:0]
12.3.3
Auto-reload register (ARTARR)
ARTARR 7 6 5 4 AR[7:0] RW 3 2 Reset value: 0000 0000 (00h) 1 0
Table 47.
Bit
ARTAAR register description
Function Counter Auto-Reload Data These bits are set and cleared by software. They are used to hold the auto-reload value which is automatically loaded in the counter when an overflow occurs. At the same time, the PWM output levels are changed according to the corresponding OPx bit in the PWMCR register.
Name
7:0
AR[7:0]
This register has two PWM management functions: - - Adjusting the PWM frequency Setting the PWM duty cycle resolution
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PWM auto-reload timer (ART) Table 48. PWM frequency versus resolution
fPWM ARTARR value 0 [ 0..127 ] [ 128..191 ] [ 192..223 ] [ 224..239 ] Resolution Min 8-bit > 7-bit > 6-bit > 5-bit > 4-bit ~0.244 kHz ~0.244 kHz ~0.488 kHz ~0.977 kHz ~1.953 kHz
ST72321Bxxx-Auto
Max 31.25 kHz 62.5 kHz 125 kHz 250 kHz 500 kHz
12.3.4
PWM control register (PWMCR)
PWMCR 7 6 OE[3:0] RW 5 4 3 2 OP[3:0] RW Reset value: 0000 0000 (00h) 1 0
Table 49.
Bit
PWMCR register description
Function
Name
7:4
PWM Output Enable These bits are set and cleared by software. They enable or disable the PWM OE[3:0] output channels independently acting on the corresponding I/O pin. 0: PWM output disabled 1: PWM output enabled OP[3:0] PWM Output Polarity These bits are set and cleared by software. They independently select the polarity of the four PWM output signals (see Table 50).
3:0
Table 50.
PWM output signal polarity selection
PWMx output level OPx(1) 0 1 0 1
Counter <= OCRx 1 0
Counter > OCRx
1. When an OPx bit is modified, the PWMx output signal polarity is immediately reversed.
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PWM auto-reload timer (ART)
12.3.5
Duty cycle registers (PWMDCRx)
PWMDCRx 7 6 5 4 DC[7:0] RW 3 2 Reset value: 0000 0000 (00h) 1 0
Table 51.
Bit 7:0
PWMDCRx register description
Function Duty Cycle Data These bits are set and cleared by software.
Name DC[7:0]
A PWMDCRx register is associated with the OCRx register of each PWM channel to determine the second edge location of the PWM signal (the first edge location is common to all channels and given by the ARTARR register). These PWMDCR registers allow the duty cycle to be set independently for each PWM channel.
12.3.6
Input capture control / status register (ARTICCSR)
ARTICCSR 7 Reserved 6 5 CS[2:1] RW 4 3 CIE[2:1] RW 2 Reset value: 0000 0000 (00h) 1 CF[2:1] RW 0
Table 52.
Bit 7:6
ARTICCSR register description
Function Reserved, always read as 0. Capture Sensitivity These bits are set and cleared by software. They determine the trigger event polarity on the corresponding input capture channel. 0: Falling edge triggers capture on channel x 1: Rising edge triggers capture on channel x
Name -
5:4
CS[2:1]
3:2
Capture Interrupt Enable These bits are set and cleared by software. They enable or disable the Input CIE[2:1] capture channel interrupts independently. 0: Input capture channel x interrupt disabled 1: Input capture channel x interrupt enabled Capture Flag These bits are set by hardware and cleared by software reading the corresponding ARTICRx register. Each CFx bit indicates that an input capture x has occurred. 0: No input capture on channel x 1: An input capture has occurred on channel x.
1:0
CF[2:1]
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PWM auto-reload timer (ART)
ST72321Bxxx-Auto
12.3.7
Input capture registers (ARTICRx)
ARTICRx 7 6 5 4 IC[7:0] RO 3 2 Reset value: 0000 0000 (00h) 1 0
Table 53.
Bit
ARTICRx register description
Function Input Capture Data These read only bits are set and cleared by hardware. An ARTICRx register contains the 8-bit auto-reload counter value transferred by the input capture channel x event.
Name
7:0
IC[7:0]
Table 54.
PWM auto-reload timer register map and reset values
7 DC7 0 DC7 0 DC7 0 DC7 0 OE3 0 EXCL 0 CA7 0 AR7 0 0 IC7 0 IC7 0 6 DC6 0 DC6 0 DC6 0 DC6 0 OE2 0 CC2 0 CA6 0 AR6 0 0 IC6 0 IC6 0 5 DC5 0 DC5 0 DC5 0 DC5 0 OE1 0 CC1 0 CA5 0 AR5 0 CS2 0 IC5 0 IC5 0 4 DC4 0 DC4 0 DC4 0 DC4 0 OE0 0 CC0 0 CA4 0 AR4 0 CS1 0 IC4 0 IC4 0 3 DC3 0 DC3 0 DC3 0 DC3 0 OP3 0 TCE 0 CA3 0 AR3 0 CIE2 0 IC3 0 IC3 0 2 DC2 0 DC2 0 DC2 0 DC2 0 OP2 0 FCRL 0 CA2 0 AR2 0 CIE1 0 IC2 0 IC2 0 1 DC1 0 DC1 0 DC1 0 DC1 0 OP1 0 RIE 0 CA1 0 AR1 0 CF2 0 IC1 0 IC1 0 0 DC0 0 DC0 0 DC0 0 DC0 0 OP0 0 OVF 0 CA0 0 AR0 0 CF1 0 IC0 0 IC0 0
Address (Hex.) Register label 0073h 0074h 0075h 0076h 0077h 0078h 0079h 007Ah 007Bh 007Ch 007Dh PWMDCR3 Reset value PWMDCR2 Reset value PWMDCR1 Reset value PWMDCR0 Reset value PWMCR Reset value ARTCSR Reset value ARTCAR Reset value ARTARR Reset value ARTICCSR Reset value ARTICR1 Reset value ARTICR2 Reset value
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ST72321Bxxx-Auto
16-bit timer
13
13.1
16-bit timer
Introduction
The timer consists of a 16-bit free-running counter driven by a programmable prescaler. It may be used for a variety of purposes, including pulse length measurement of up to two input signals (input capture) or generation of up to two output waveforms (output compare and PWM). Pulse lengths and waveform periods can be modulated from a few microseconds to several milliseconds using the timer prescaler and the CPU clock prescaler. Some ST7 devices have two on-chip 16-bit timers. They are completely independent, and do not share any resources. They are synchronized after an MCU reset as long as the timer clock frequencies are not modified. This description covers one or two 16-bit timers. In ST7 devices with two timers, register names are prefixed with TA (Timer A) or TB (Timer B).
13.2
Main features

Programmable prescaler: fCPU divided by 2, 4 or 8 Overflow status flag and maskable interrupt External clock input (must be at least four times slower than the CPU clock speed) with the choice of active edge 1 or 2 Output Compare functions each with: - - - - 2 dedicated 16-bit registers 2 dedicated programmable signals 2 dedicated status flags 1 dedicated maskable interrupt 2 dedicated 16-bit registers 2 dedicated active edge selection signals 2 dedicated status flags 1 dedicated maskable interrupt
1 or 2 Input Capture functions each with: - - - -

Pulse Width Modulation mode (PWM) One Pulse mode Reduced Power mode 5 alternate functions on I/O ports (ICAP1, ICAP2, OCMP1, OCMP2, EXTCLK)(a)
The block diagram is shown in Figure 41. Note: When reading an input signal on a non-bonded pin, the value will always be `1'.
a. Some timer pins may not be available (not bonded) in some ST7 devices. Refer to the device pinout description.
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16-bit timer
ST72321Bxxx-Auto
13.3
13.3.1
Functional description
Counter
The main block of the Programmable Timer is a 16-bit free running upcounter and its associated 16-bit registers. The 16-bit registers are made up of two 8-bit registers called high and low. Counter Register (CR)

Counter High Register (CHR) is the most significant byte (MS Byte) Counter Low Register (CLR) is the least significant byte (LS Byte) Alternate Counter High Register (ACHR) is the most significant byte (MS Byte) Alternate Counter Low Register (ACLR) is the least significant byte (LS Byte)
Alternate Counter Register (ACR)

These two read-only 16-bit registers contain the same value but with the difference that reading the ACLR register does not clear the TOF bit (Timer overflow flag), located in the Status register (SR) (see note at the end of paragraph entitled 16-bit read sequence). Writing in the CLR register or ACLR register resets the free running counter to the FFFCh value. Both counters have a reset value of FFFCh (this is the only value which is reloaded in the 16-bit timer). The reset value of both counters is also FFFCh in One Pulse mode and PWM mode. The timer clock depends on the clock control bits of the CR2 register, as illustrated in Table 60: Timer clock selection. The value in the counter register repeats every 131072, 262144 or 524288 CPU clock cycles depending on the CC[1:0] bits. The timer frequency can be fCPU/2, fCPU/4, fCPU/8 or an external frequency.
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ST72321Bxxx-Auto Figure 41. Timer block diagram
ST7 INTERNAL BUS fCPU
16-bit timer
MCU-PERIPHERAL INTERFACE
8 low
8 high
8-bit buffer
high
8 low
8 high
8 low
8 high
8 low
8 high
8 low 16
8
EXEDG
16
1/2 1/4 1/8 EXTCLK pin
COUNTER REGISTER ALTERNATE COUNTER REGISTER
16
OUTPUT COMPARE REGISTER 1
OUTPUT COMPARE REGISTER 2
INPUT CAPTURE REGISTER 1
16
INPUT CAPTURE REGISTER 2
CC[1:0] TIMER INTERNAL BUS
16 16
OVERFLOW DETECT CIRCUIT
OUTPUT COMPARE CIRCUIT
EDGE DETECT CIRCUIT1
ICAP1 pin
6
EDGE DETECT CIRCUIT2
ICAP2 pin
LATCH1
ICF1 OCF1 TOF ICF2 OCF2 TIMD 0 0
OCMP1 pin OCMP2 pin
(Control/Status Register) CSR
LATCH2
ICIE
OCIE TOIE FOLV2 FOLV1 OLVL2 IEDG1 OLVL1
OC1E OC2E
OPM
PWM
CC1
CC0
IEDG2 EXEDG
(Control Register 1) CR1
(Control Register 2) CR2
(1)
TIMER INTERRUPT
1. If IC, OC and TO interrupt request have separate vectors, then the last OR is not present (see device interrupt vector table).
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16-bit timer
ST72321Bxxx-Auto
16-bit read sequence
The 16-bit read sequence (from either the Counter Register or the Alternate Counter Register) is illustrated in Figure 42. Figure 42. 16-bit read sequence
Beginning of the sequence At t0 Read MS Byte Other instructions Read LS Byte Returns the buffered LS Byte value at t0 LS Byte is buffered
At t0 +Dt
Sequence completed
The user must read the MS Byte first; the LS Byte value is then buffered automatically. This buffered value remains unchanged until the 16-bit read sequence is completed, even if the user reads the MS Byte several times. After a complete reading sequence, if only the CLR register or ACLR register are read, they return the LS Byte of the count value at the time of the read. Whatever timer mode is used (input capture, output compare, one pulse mode or PWM mode) an overflow occurs when the counter rolls over from FFFFh to 0000h, after which

the TOF bit of the SR register is set a timer interrupt is generated if - - the TOIE bit of the CR1 register is set and the I bit of the CC register is cleared
If one of these conditions is false, the interrupt remains pending to be issued as soon as they are both true. Clearing the overflow interrupt request is done in two steps: 1. 2. Note: Reading the SR register while the TOF bit is set An access (read or write) to the CLR register
The TOF bit is not cleared by accesses to ACLR register. The advantage of accessing the ACLR register rather than the CLR register is that it allows simultaneous use of the overflow function and reading the free running counter at random times (for example, to measure elapsed time) without the risk of clearing the TOF bit erroneously. The timer is not affected by Wait mode. In Halt mode, the counter stops counting until the mode is exited. Counting then resumes from the previous count (MCU awakened by an interrupt) or from the reset count (MCU awakened by a Reset).
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ST72321Bxxx-Auto
16-bit timer
13.3.2
External clock
The external clock (where available) is selected if CC0 = 1 and CC1 = 1 in the CR2 register. The status of the EXEDG bit in the CR2 register determines the type of level transition on the external clock pin EXTCLK that will trigger the free running counter. The counter is synchronized with the falling edge of the internal CPU clock. A minimum of four falling edges of the CPU clock must occur between two consecutive active edges of the external clock; thus, the external clock frequency must be less than a quarter of the CPU clock frequency. Figure 43. Counter timing diagram, internal clock divided by 2
CPU CLOCK INTERNAL RESET TIMER CLOCK COUNTER REGISTER TIMER OVERFLOW FLAG (TOF) FFFD FFFE FFFF 0000 0001 0002 0003
Figure 44. Counter timing diagram, internal clock divided by 4
CPU CLOCK INTERNAL RESET TIMER CLOCK COUNTER REGISTER TIMER OVERFLOW FLAG (TOF) FFFC FFFD 0000 0001
Figure 45. Counter timing diagram, internal clock divided by 8
CPU CLOCK INTERNAL RESET TIMER CLOCK COUNTER REGISTER TIMER OVERFLOW FLAG (TOF) FFFC FFFD 0000
Note:
The MCU is in reset state when the internal reset signal is high; when it is low the MCU is running.
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16-bit timer
ST72321Bxxx-Auto
13.3.3
Input capture
In this section, the index, i, may be 1 or 2 because there are two input capture functions in the 16-bit timer. The two 16-bit input capture registers (IC1R and IC2R) are used to latch the value of the free running counter after a transition is detected on the ICAPi pin (see Figure 46).
MS Byte ICiR ICiHR LS Byte ICiLR
ICiR register is a read-only register. The active transition is software programmable through the IEDGi bit of Control Registers (CRi). Timing resolution is one count of the free running counter: (fCPU/CC[1:0]). Procedure: To use the input capture function select the following in the CR2 register:

Select the timer clock (CC[1:0]) (see Table 60: Timer clock selection). Select the edge of the active transition on the ICAP2 pin with the IEDG2 bit (the ICAP2 pin must be configured as floating input or input with pull-up without interrupt if this configuration is available). Set the ICIE bit to generate an interrupt after an input capture coming from either the ICAP1 pin or the ICAP2 pin Select the edge of the active transition on the ICAP1 pin with the IEDG1 bit (the ICAP1pin must be configured as floating input or input with pull-up without interrupt if this configuration is available). ICFi bit is set. The ICiR register contains the value of the free running counter on the active transition on the ICAPi pin (see Figure 47). A timer interrupt is generated if the ICIE bit is set and the I bit is cleared in the CC register. Otherwise, the interrupt remains pending until both conditions become true.
And select the following in the CR1 register:

When an input capture occurs:

Clearing the input capture interrupt request (that is, clearing the ICFi bit) is done in two steps: 1. 2. Note: 1 2 3 4 Reading the SR register while the ICFi bit is set An access (read or write) to the ICiLR register
After reading the ICiHR register, transfer of input capture data is inhibited and ICFi will never be set until the ICiLR register is also read. The ICiR register contains the free running counter value which corresponds to the most recent input capture. The two input capture functions can be used together even if the timer also uses the two output compare functions. In One pulse Mode and PWM mode only Input Capture 2 can be used.
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ST72321Bxxx-Auto 5 6 7 8
16-bit timer
The alternate inputs (ICAP1 and ICAP2) are always directly connected to the timer. So any transitions on these pins activates the input capture function. Moreover if one of the ICAPi pins is configured as an input and the second one as an output, an interrupt can be generated if the user toggles the output pin and if the ICIE bit is set. This can be avoided if the input capture function i is disabled by reading the ICiHR (see note 1). The TOF bit can be used with interrupt generation in order to measure events that go beyond the timer range (FFFFh).
Figure 46. Input capture block diagram
ICAP1 pin EDGE DETECT ICAP2 pin CIRCUIT2 EDGE DETECT CIRCUIT1 ICIE
(Control Register 1) CR1 IEDG1
(Status Register) SR IC2R Register IC1R Register ICF1 ICF2 0 0 0
16-BIT 16-BIT FREE RUNNING COUNTER CC1
(Control Register 2) CR2 CC0 IEDG2
Figure 47. Input capture timing diagram
TIMER CLOCK COUNTER REGISTER ICAPi PIN ICAPi FLAG ICAPi REGISTER FF03 FF01 FF02 FF03
Note: The rising edge is the active edge.
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16-bit timer
ST72321Bxxx-Auto
13.3.4
Output compare
In this section, the index, i, may be 1 or 2 because there are two output compare functions in the 16-bit timer. This function can be used to control an output waveform or indicate when a period of time has elapsed. When a match is found between the Output Compare register and the free running counter, the output compare function:

Assigns pins with a programmable value if the OCiE bit is set Sets a flag in the status register Generates an interrupt if enabled
Two 16-bit registers Output Compare Register 1 (OC1R) and Output Compare Register 2 (OC2R) contain the value to be compared to the counter register each timer clock cycle.
MS byte OCiR OCiHR LS byte OCiLR
These registers are readable and writable and are not affected by the timer hardware. A reset event changes the OCiR value to 8000h. Timing resolution is one count of the free running counter: (fCPU/CC[1:0]).
Procedure
To use the output compare function, select the following in the CR2 register:

Set the OCiE bit if an output is needed then the OCMPi pin is dedicated to the output compare i signal. Select the timer clock (CC[1:0]) (see Table 60: Timer clock selection). Select the OLVLi bit to applied to the OCMPi pins after the match occurs. Set the OCIE bit to generate an interrupt if it is needed. OCFi bit is set. The OCMPi pin takes OLVLi bit value (OCMPi pin latch is forced low during reset). A timer interrupt is generated if the OCIE bit is set in the CR1 register and the I bit is cleared in the CC register (CC).
And select the following in the CR1 register:

When a match is found between OCRi register and CR register:

The OCiR register value required for a specific timing application can be calculated using the following formula: t * fCPU OCiR =
PRESC
Where: t fCPU = Output compare period (in seconds) = CPU clock frequency (in hertz)
PRESC = Timer prescaler factor (2, 4 or 8 depending on CC[1:0] bits; see Table 60: Timer clock selection)
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ST72321Bxxx-Auto If the timer clock is an external clock, the formula is: OCiR = t * fEXT Where: t fCPU 1. 2. = Output compare period (in seconds) = External timer clock frequency (in hertz)
16-bit timer
Clearing the output compare interrupt request (that is, clearing the OCFi bit) is done by: Reading the SR register while the OCFi bit is set An access (read or write) to the OCiLR register
The following procedure is recommended to prevent the OCFi bit from being set between the time it is read and the write to the OCiR register:

Write to the OCiHR register (further compares are inhibited). Read the SR register (first step of the clearance of the OCFi bit, which may be already set). Write to the OCiLR register (enables the output compare function and clears the OCFi bit).
Note:
1 2 3
After a processor write cycle to the OCiHR register, the output compare function is inhibited until the OCiLR register is also written. If the OCiE bit is not set, the OCMPi pin is a general I/O port and the OLVLi bit will not appear when a match is found but an interrupt could be generated if the OCIE bit is set. In both internal and external clock modes, OCFi and OCMPi are set while the counter value equals the OCiR register value (see Figure 49 on page 112 for an example with fCPU/2 and Figure 50 on page 112 for an example with fCPU/4). This behavior is the same in OPM or PWM mode. The output compare functions can be used both for generating external events on the OCMPi pins even if the input capture mode is also used. The value in the 16-bit OCiR register and the OLVi bit should be changed after each successful comparison in order to control an output waveform or establish a new elapsed timeout.
4 5
13.3.5
Forced compare output capability
When the FOLVi bit is set by software, the OLVLi bit is copied to the OCMPi pin. The OLVi bit has to be toggled in order to toggle the OCMPi pin when it is enabled (OCiE bit = 1). The OCFi bit is then not set by hardware, and thus no interrupt request is generated. The FOLVLi bits have no effect in both one pulse mode and PWM mode.
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16-bit timer Figure 48. Output compare block diagram
ST72321Bxxx-Auto
16-BIT FREE RUNNING COUNTER 16-bit
OC1E OC2E
CC1
CC0
(Control Register 2) CR2
(Control Register 1) CR1 OUTPUT COMPARE CIRCUIT OCIE FOLV2 FOLV1 OLVL2 OLVL1 Latch 1 OCMP1 pin
16-bit OC1R Register
16-bit
Latch 2 OCF1 OCF2 0 0 0
OCMP2 pin
OC2R Register
(Status Register) SR
Figure 49. Output compare timing diagram, fTIMER = fCPU/2
INTERNAL CPU CLOCK TIMER CLOCK COUNTER REGISTER OUTPUT COMPARE REGISTER i (OCRi) OUTPUT COMPARE FLAG i (OCFi) OCMPi PIN (OLVLi = 1) 2ECF 2ED0 2ED1 2ED2 2ED3 2ED4 2ED3
Figure 50. Output compare timing diagram, fTIMER = fCPU/4
INTERNAL CPU CLOCK TIMER CLOCK COUNTER REGISTER OUTPUT COMPARE REGISTER i (OCRi) OUTPUT COMPARE FLAG i (OCFi) OCMPi PIN (OLVLi = 1) 2ECF 2ED0 2ED1 2ED2 2ED3 2ED4 2ED3
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ST72321Bxxx-Auto
16-bit timer
13.3.6
One Pulse mode
One Pulse mode enables the generation of a pulse when an external event occurs. This mode is selected via the OPM bit in the CR2 register. The one pulse mode uses the Input Capture1 function and the Output Compare1 function.
Procedure
To use one pulse mode: 1. 2. Load the OC1R register with the value corresponding to the length of the pulse (using the appropriate formula below according to the timer clock source used). Select the following in the CR1 register: - - - 3. Using the OLVL1 bit, select the level to be applied to the OCMP1 pin after the pulse. Using the OLVL2 bit, select the level to be applied to the OCMP1 pin during the pulse. Select the edge of the active transition on the ICAP1 pin with the IEDG1 bit (the ICAP1 pin must be configured as floating input). Set the OC1E bit, the OCMP1 pin is then dedicated to the Output Compare 1 function. Set the OPM bit. Select the timer clock CC[1:0] (see Table 60: Timer clock selection).
Select the following in the CR2 register: - - -
Then, on a valid event on the ICAP1 pin, the counter is initialized to FFFCh and OLVL2 bit is loaded on the OCMP1 pin, the ICF1 bit is set and the value FFFDh is loaded in the IC1R register. Figure 51. One pulse mode cycle flowchart
When event occurs on ICAP1
ICR1 = Counter OCMP1 = OLVL2 Counter is reset to FFFCh ICF1 bit is set
When counter = OC1R
OCMP1 = OLVL1
Because the ICF1 bit is set when an active edge occurs, an interrupt can be generated if the ICIE bit is set. Clearing the input capture interrupt request (that is, clearing the ICFi bit) is done in two steps: 1. 2. Reading the SR register while the ICFi bit is set An access (read or write) to the ICiLR register
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16-bit timer
ST72321Bxxx-Auto The OC1R register value required for a specific timing application can be calculated using the following formula: t * fCPU - 5 OCiR value =
PRESC
Where: t fCPU = Pulse period (in seconds) = CPU clock frequency (in hertz)
PRESC = Timer prescaler factor (2, 4 or 8 depending on the CC[1:0] bits; see Table 60: Timer clock selection) If the timer clock is an external clock the formula is: OCiR = t * fEXT - 5 Where: t fEXT = Pulse period (in seconds) = External clock frequency (in hertz)
When the value of the counter is equal to the value of the contents of the OC1R register, the OLVL1 bit is output on the OCMP1 pin (see Figure 52). Note: 1 2 3 4 The OCF1 bit cannot be set by hardware in one pulse mode but the OCF2 bit can generate an Output Compare interrupt. When the Pulse Width Modulation (PWM) and One Pulse Mode (OPM) bits are both set, the PWM mode is the only active one. If OLVL1 = OLVL2 a continuous signal will be seen on the OCMP1 pin. The ICAP1 pin cannot be used to perform input capture. The ICAP2 pin can be used to perform input capture (ICF2 can be set and IC2R can be loaded) but the user must take care that the counter is reset each time a valid edge occurs on the ICAP1 pin and ICF1 can also generates interrupt if ICIE is set. When one pulse mode is used OC1R is dedicated to this mode. Nevertheless OC2R and OCF2 can be used to indicate a period of time has been elapsed but cannot generate an output waveform because the level OLVL2 is dedicated to the one pulse mode. Figure 52. One pulse mode timing example
5
IC1R COUNTER 01F8 FFFC FFFD FFFE
01F8 2ED0 2ED1 2ED2 2ED3
2ED3 FFFC FFFD
ICAP1 OLVL2 compare1 Note: IEDG1 = 1, OC1R = 2ED0h, OLVL1 = 0, OLVL2 = 1 OLVL1 OLVL2
OCMP1
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ST72321Bxxx-Auto
16-bit timer
Figure 53. Pulse width modulation mode timing example with 2 output compare functions
COUNTER 34E2 FFFC FFFD FFFE OCMP1 OLVL2
2ED0 2ED1 2ED2
34E2
FFFC
OLVL1
OLVL2
compare2
compare1
compare2
Note: OC1R = 2ED0h, OC2R = 34E2, OLVL1 = 0, OLVL2 = 1
Note:
On timers with only one Output Compare register, a fixed frequency PWM signal can be generated using the output compare and the counter overflow to define the pulse length.
13.3.7
Pulse width modulation mode
Pulse Width Modulation (PWM) mode enables the generation of a signal with a frequency and pulse length determined by the value of the OC1R and OC2R registers. Pulse Width Modulation mode uses the complete Output Compare 1 function plus the OC2R register, and so this functionality cannot be used when PWM mode is activated. In PWM mode, double buffering is implemented on the output compare registers. Any new values written in the OC1R and OC2R registers are taken into account only at the end of the PWM period (OC2) to avoid spikes on the PWM output pin (OCMP1).
Procedure
To use pulse width modulation mode: 1. 2. Load the OC2R register with the value corresponding to the period of the signal using the appropriate formula below according to the timer clock source used. Load the OC1R register with the value corresponding to the period of the pulse if OLVL1 = 0 and OLVL2 = 1 using the appropriate formula below according to the timer clock source used. Select the following in the CR1 register: - - 4. Using the OLVL1 bit, select the level to be applied to the OCMP1 pin after a successful comparison with the OC1R register. Using the OLVL2 bit, select the level to be applied to the OCMP1 pin after a successful comparison with the OC2R register. Set OC1E bit: the OCMP1 pin is then dedicated to the output compare 1 function. Set the PWM bit. Select the timer clock (CC[1:0]) (see Table 60: Timer clock selection).
3.
Select the following in the CR2 register: - - -
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16-bit timer Figure 54. Pulse width modulation cycle flowchart
ST72321Bxxx-Auto
When Counter = OC1R
OCMP1 = OLVL1
When Counter = OC2R
OCMP1 = OLVL2 Counter is reset to FFFCh ICF1 bit is set
If OLVL1 = 1 and OLVL2 = 0 the length of the positive pulse is the difference between the OC2R and OC1R registers. If OLVL1 = OLVL2 a continuous signal will be seen on the OCMP1 pin. The OCiR register value required for a specific timing application can be calculated using the following formula: tf OCiR value = * CPU - 5
PRESC
Where: t fCPU = Signal or pulse period (in seconds) = CPU clock frequency (in hertz)
PRESC = Timer prescaler factor (2, 4 or 8 depending on CC[1:0] bits; see Table 60: Timer clock selection) If the timer clock is an external clock the formula is: OCiR = t * fEXT -5 Where: t fEXT Note: 1 2 3 4 = Signal or pulse period (in seconds) = External timer clock frequency (in hertz)
The Output Compare 2 event causes the counter to be initialized to FFFCh (see Figure 53). After a write instruction to the OCiHR register, the output compare function is inhibited until the OCiLR register is also written. The OCF1 and OCF2 bits cannot be set by hardware in PWM mode therefore the Output Compare interrupt is inhibited. The ICF1 bit is set by hardware when the counter reaches the OC2R value and can produce a timer interrupt if the ICIE bit is set and the I bit is cleared. In PWM mode the ICAP1 pin cannot be used to perform input capture because it is disconnected to the timer. The ICAP2 pin can be used to perform input capture (ICF2 can be set and IC2R can be loaded) but the user must take care that the counter is reset each period and ICF1 can also generates interrupt if ICIE is set. When the Pulse Width Modulation (PWM) and One Pulse Mode (OPM) bits are both set, the PWM mode is the only active one.
5
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ST72321Bxxx-Auto
16-bit timer
13.4
Low power modes
Table 55.
Mode Wait
Effect of low power modes on 16-bit timer
Effect No effect on 16-bit timer. Timer interrupts cause the device to exit from Wait mode. 16-bit timer registers are frozen. In Halt mode, the counter stops counting until Halt mode is exited. Counting resumes from the previous count when the MCU is woken up by an interrupt with "exit from Halt mode" capability or from the counter reset value when the MCU is woken up by a RESET. If an input capture event occurs on the ICAPi pin, the input capture detection circuitry is armed. Consequently, when the MCU is woken up by an interrupt with "exit from Halt mode" capability, the ICFi bit is set, and the counter value present when exiting from Halt mode is captured into the ICiR register.
Halt
13.5
Interrupts
Table 56. 16-bit timer interrupt control/wake-up capability
Interrupt event Input Capture 1 event/Counter reset in PWM mode Input Capture 2 event Output Compare 1 event (not available in PWM mode) Output Compare 2 event (not available in PWM mode) Timer Overflow event Event flag ICF1 ICIE ICF2 OCF1 OCIE OCF2 TOF TOIE Yes No Enable control bit Exit from Wait Exit from Halt
Note:
The 16-bit timer interrupt events are connected to the same interrupt vector (see Chapter 7: Interrupts on page 55). These events generate an interrupt if the corresponding Enable Control Bit is set and the interrupt mask in the CC register is reset (RIM instruction).
13.6
Summary of timer modes
Table 57.
Modes
Timer modes
Timer resources Input Capture 1 Input Capture 2 Output Compare 1 Output Compare 2
Input Capture (1 and/or 2) Yes Output Compare (1 and/or 2) Yes Yes Yes
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16-bit timer Table 57.
Modes
ST72321Bxxx-Auto Timer modes
Timer resources Input Capture 1 Input Capture 2 Not recommended(1) No PWM mode Not recommended(3) No No Output Compare 1 Output Compare 2 Partially(2)
One Pulse mode
1. See Note 4 in Section 13.3.6 One Pulse mode 2. See Note 5 in Section 13.3.6 One Pulse mode 3. See Note 4 in Section 13.3.7 Pulse width modulation mode
13.7
16-bit timer registers
Each timer is associated with 3 control and status registers, and with 6 pairs of data registers (16-bit values) relating to the 2 input captures, the 2 output compares, the counter and the alternate counter.
13.7.1
Control register 1 (CR1)
CR1 7 ICIE RW 6 OCIE RW 5 TOIE RW 4 FOLV2 RW 3 FOLV1 RW 2 OLVL2 RW Reset value: 0000 0000 (00h) 1 IEDG1 RW 0 OLVL1 RW
Table 58.
Bit Name
CR1 register description
Function Input Capture Interrupt Enable 0: Interrupt is inhibited 1: A timer interrupt is generated whenever the ICF1 or ICF2 bit of the SR register is set. Output Compare Interrupt Enable 0: Interrupt is inhibited 1: A timer interrupt is generated whenever the OCF1 or OCF2 bit of the SR register is set. Timer Overflow Interrupt Enable 0: Interrupt is inhibited 1: A timer interrupt is enabled whenever the TOF bit of the SR register is set.
7
ICIE
6
OCIE
5
TOIE
4
Forced Output Compare 2 This bit is set and cleared by software. FOLV2 0: No effect on the OCMP2 pin 1: Forces the OLVL2 bit to be copied to the OCMP2 pin, if the OC2E bit is set and even if there is no successful comparison
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ST72321Bxxx-Auto Table 58.
Bit Name
16-bit timer CR1 register description (continued)
Function
3
Forced Output Compare 1 This bit is set and cleared by software. FOLV1 0: No effect on the OCMP1 pin 1: Forces OLVL1 to be copied to the OCMP1 pin, if the OC1E bit is set and even if there is no successful comparison Output Level 2 This bit is copied to the OCMP2 pin whenever a successful comparison occurs with OLVL2 the OC2R register and OCxE is set in the CR2 register. This value is copied to the OCMP1 pin in One Pulse Mode and Pulse Width Modulation mode. Input Edge 1 This bit determines which type of level transition on the ICAP1 pin will trigger the IEDG1 capture. 0: A falling edge triggers the capture. 1: A rising edge triggers the capture. OLVL1 Output Level 1 The OLVL1 bit is copied to the OCMP1 pin whenever a successful comparison occurs with the OC1R register and the OC1E bit is set in the CR2 register.
2
1
0
13.7.2
Control register 2 (CR2)
CR2 7 OC1E RW 6 OC2E RW 5 OPM RW 4 PWM RW 3 CC[1:0] RW 2 Reset value: 0000 0000 (00h) 1 IEDG2 RW 0 EXEDG RW
Table 59.
Bit Name
CR2 register description
Function Output Compare 1 Pin Enable This bit is used only to output the signal from the timer on the OCMP1 pin (OLV1 in Output Compare mode, both OLV1 and OLV2 in PWM and one-pulse mode). Whatever the value of the OC1E bit, the Output Compare 1 function of the timer remains active. 0: OCMP1 pin alternate function disabled (I/O pin free for general-purpose I/O) 1: OCMP1 pin alternate function enabled Output Compare 2 Pin Enable This bit is used only to output the signal from the timer on the OCMP2 pin (OLV2 in Output Compare mode). Whatever the value of the OC2E bit, the Output Compare 2 function of the timer remains active. 0: OCMP2 pin alternate function disabled (I/O pin free for general-purpose I/O) 1: OCMP2 pin alternate function enabled
7
OC1E
6
OC2E
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16-bit timer Table 59.
Bit Name
ST72321Bxxx-Auto CR2 register description (continued)
Function One Pulse Mode 0: One Pulse Mode is not active. 1: One Pulse Mode is active, the ICAP1 pin can be used to trigger one pulse on the OCMP1 pin; the active transition is given by the IEDG1 bit. The length of the generated pulse depends on the contents of the OC1R register. Pulse Width Modulation 0: PWM mode is not active. 1: PWM mode is active, the OCMP1 pin outputs a programmable cyclic signal; the length of the pulse depends on the value of OC1R register; the period depends on the value of OC2R register. Clock Control The timer clock mode depends on these bits (see Table 60).
5
OPM
4
PWM
3:2 CC[1:0]
1
Input Edge 2 This bit determines which type of level transition on the ICAP2 pin will trigger the IEDG2 capture. 0: A falling edge triggers the capture. 1: A rising edge triggers the capture. External Clock Edge This bit determines which type of level transition on the external clock pin EXTCLK EXEDG will trigger the counter register. 0: A falling edge triggers the counter register. 1: A rising edge triggers the counter register.
0
Table 60.
Timer clock selection
Timer clock
fCPU / 4 fCPU / 2 fCPU / 8
CC1 0 0 1 1
CC0 0 1 0 1
External clock (where available)(1)
1. If the external clock pin is not available, programming the external clock configuration stops the counter.
13.7.3
Control/status register (CSR)
CSR 7 ICF1 RO 6 OCF1 RO 5 TOF RO 4 ICF2 RO 3 OCF2 RO 2 TIMD RW Reset value: xxxx x0xx (xxh) 1 Reserved 0
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ST72321Bxxx-Auto Table 61.
Bit Name
16-bit timer CSR register description
Function Input Capture Flag 1 0: No input capture (reset value) 1: An input capture has occurred on the ICAP1 pin or the counter has reached the OC2R value in PWM mode. To clear this bit, first read the SR register, then read or write the low byte of the IC1R (IC1LR) register. Output Compare Flag 1 0: No match (reset value) 1: The content of the free running counter has matched the content of the OC1R register. To clear this bit, first read the SR register, then read or write the low byte of the OC1R (OC1LR) register. Timer Overflow Flag 0: No timer overflow (reset value) 1: The free running counter rolled over from FFFFh to 0000h. To clear this bit, first read the SR register, then read or write the low byte of the CR (CLR) register. Note: Reading or writing the ACLR register does not clear TOF. Input Capture Flag 2 0: No input capture (reset value). 1: An input capture has occurred on the ICAP2 pin. To clear this bit, first read the SR register, then read or write the low byte of the IC2R (IC2LR) register. Output Compare Flag 2 0: No match (reset value) 1: The content of the free running counter has matched the content of the OC2R register. To clear this bit, first read the SR register, then read or write the low byte of the OC2R (OC2LR) register. Timer disable This bit is set and cleared by software. When set, it freezes the timer prescaler and counter and disabled the output functions (OCMP1 and OCMP2 pins) to reduce power consumption. Access to the timer registers is still available, allowing the timer configuration to be changed, or the counter reset, while it is disabled. 0: Timer enabled 1: Timer prescaler, counter and outputs disabled Reserved, must be kept cleared
7
ICF1
6
OCF1
5
TOF
4
ICF2
3
OCF2
2
TIMD
1:0
-
13.7.4
Input capture 1 high register (IC1HR)
This is an 8-bit read only register that contains the high part of the counter value (transferred by the input capture 1 event).
IC1HR 7 MSB RO RO RO RO RO RO RO 6 5 4 3 2 Reset value: Undefined 1 0 LSB RO
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16-bit timer
ST72321Bxxx-Auto
13.7.5
Input capture 1 low register (IC1LR)
This is an 8-bit read only register that contains the low part of the counter value (transferred by the input capture 1 event).
IC1LR 7 MSB RO RO RO RO RO RO RO 6 5 4 3 2 Reset value: Undefined 1 0 LSB RO
13.7.6
Output compare 1 high register (OC1HR)
This is an 8-bit register that contains the high part of the value to be compared to the CHR register.
OC1HR 7 MSB RW RW RW RW RW RW RW 6 5 4 3 2 Reset value: 1000 0000 (80h) 1 0 LSB RW
13.7.7
Output compare 1 low register (OC1LR)
This is an 8-bit register that contains the low part of the value to be compared to the CLR register.
OC1LR 7 MSB RW RW RW RW RW RW RW 6 5 4 3 2 Reset value: 0000 0000 (00h) 1 0 LSB RW
13.7.8
Output compare 2 high register (OC2HR)
This is an 8-bit register that contains the high part of the value to be compared to the CHR register.
OC2HR 7 MSB RW RW RW RW RW RW RW 6 5 4 3 2 Reset value: 1000 0000 (80h) 1 0 LSB RW
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ST72321Bxxx-Auto
16-bit timer
13.7.9
Output compare 2 low register (OC2LR)
This is an 8-bit register that contains the low part of the value to be compared to the CLR register.
OC2LR 7 MSB RW RW RW RW RW RW RW 6 5 4 3 2 Reset value: 0000 0000 (00h) 1 0 LSB RW
13.7.10
Counter high register (CHR)
This is an 8-bit register that contains the high part of the counter value.
CHR 7 MSB RO RO RO RO RO RO RO 6 5 4 3 2 Reset value: 1111 1111 (FFh) 1 0 LSB RO
13.7.11
Counter low register (CLR)
This is an 8-bit register that contains the low part of the counter value. A write to this register resets the counter. An access to this register after accessing the CSR register clears the TOF bit.
CLR 7 MSB RO RO RO RO RO RO RO 6 5 4 3 2 Reset value: 1111 1100 (FCh) 1 0 LSB RO
13.7.12
Alternate counter high register (ACHR)
This is an 8-bit register that contains the high part of the counter value.
ACHR 7 MSB RO RO RO RO RO RO RO 6 5 4 3 2 Reset value: 1111 1111 (FFh) 1 0 LSB RO
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16-bit timer
ST72321Bxxx-Auto
13.7.13
Alternate counter low register (ACLR)
This is an 8-bit register that contains the low part of the counter value. A write to this register resets the counter. An access to this register after an access to CSR register does not clear the TOF bit in the CSR register.
ACLR 7 MSB RO RO RO RO RO RO RO 6 5 4 3 2 Reset value: 1111 1100 (FCh) 1 0 LSB RO
13.7.14
Input capture 2 high register (IC2HR)
This is an 8-bit read only register that contains the high part of the counter value (transferred by the Input Capture 2 event).
IC2HR 7 MSB RO RO RO RO RO RO RO 6 5 4 3 2 Reset value: Undefined 1 0 LSB RO
13.7.15
Input capture 2 low register (IC2LR)
This is an 8-bit read only register that contains the low part of the counter value (transferred by the Input Capture 2 event).
IC2LR 7 MSB RO RO RO RO RO RO RO 6 5 4 3 2 Reset value: Undefined 1 0 LSB RO
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ST72321Bxxx-Auto Table 62.
Address (Hex.)
16-bit timer 16-bit timer register map and reset values
Register label 7 ICIE 0 OC1E 0 ICF1 x MSB x MSB x MSB 1 MSB 0 MSB 1 MSB 0 MSB 1 MSB 1 MSB 1 MSB 1 MSB x MSB x 6 OCIE 0 OC2E 0 OCF1 x x x 0 0 0 0 1 1 1 1 x x 5 TOIE 0 OPM 0 TOF x x x 0 0 0 0 1 1 1 1 x x 4 FOLV2 0 PWM 0 ICF2 x x x 0 0 0 0 1 1 1 1 x x 3 FOLV1 0 CC1 0 OCF2 x x x 0 0 0 0 1 1 1 1 x x 2 1 0
Timer A: 32 CR1 Timer B: 42 Reset value Timer A: 31 CR2 Timer B: 41 Reset value Timer A: 33 CSR Timer B: 43 Reset value Timer A: 34 IC1HR Timer B: 44 Reset value Timer A: 35 IC1LR Timer B: 45 Reset value Timer A: 36 OC1HR Timer B: 46 Reset value Timer A: 37 OC1LR Timer B: 47 Reset value Timer A: 3E OC2HR Timer B: 4E Reset value Timer A: 3F OC2LR Timer B: 4F Reset value Timer A: 38 CHR Timer B: 48 Reset value Timer A: 39 CLR Timer B: 49 Reset value Timer A: 3A ACHR Timer B: 4A Reset value Timer A: 3B ACLR Timer B: 4B Reset value Timer A: 3C IC2HR Timer B: 4C Reset value Timer A: 3D IC2LR Timer B: 4D Reset value
OLVL2 IEDG1 OLVL1 0 0 0 CC0 0 TIMD 0 x x 0 0 0 0 1 1 1 1 x x IEDG2 EXEDG 0 0 x x x 0 0 0 0 1 0 1 0 x x x LSB x LSB x LSB 0 LSB 0 LSB 0 LSB 0 LSB 1 LSB 0 LSB 1 LSB 0 LSB x LSB x
Related documentation
SCI software communications using 16-bit timer (AN 973) Real-time Clock with ST7 Timer Output Compare (AN 974) Driving a buzzer through the ST7 Timer PWM function (AN 976) Using ST7 PWM signal to generate analog input (sinusoid) (AN1041) UART emulation software (AN1046) PWM duty cycle switch implementing true 0 or 100 per cent duty cycle (AN1078) Starting a PWM signal directly at high level using the ST7 16-bit timer (AN1504)
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Serial peripheral interface (SPI)
ST72321Bxxx-Auto
14
14.1
Serial peripheral interface (SPI)
Introduction
The Serial Peripheral Interface (SPI) allows full-duplex, synchronous, serial communication with external devices. An SPI system may consist of a master and one or more slaves however the SPI interface cannot be a master in a multimaster system.
14.2
Main features

Full duplex synchronous transfers (on 3 lines) Simplex synchronous transfers (on 2 lines) Master or slave operation 6 master mode frequencies (fCPU/4 max.) fCPU/2 max. slave mode frequency (see note) SS Management by software or hardware Programmable clock polarity and phase End of transfer interrupt flag Write collision, Master Mode Fault and Overrun flags
Note:
In slave mode, continuous transmission is not possible at maximum frequency due to the software overhead for clearing status flags and to initiate the next transmission sequence.
14.3
General description
Figure 55 shows the serial peripheral interface (SPI) block diagram. There are three registers:

SPI Control Register (SPICR) SPI Control/Status Register (SPICSR) SPI Data Register (SPIDR) MISO (Master In / Slave Out data) MOSI (Master Out / Slave In data) SCK (Serial Clock out by SPI masters and input by SPI slaves) SS (Slave select): This input signal acts as a `chip select' to let the SPI master communicate with slaves individually and to avoid contention on the data lines. Slave SS inputs can be driven by standard I/O ports on the master MCU.
The SPI is connected to external devices through four pins:

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ST72321Bxxx-Auto Figure 55. Serial peripheral interface block diagram
Serial peripheral interface (SPI)
Data/Address Bus
SPIDR
Read Read Buffer Interrupt request
MOSI MISO 8-bit Shift Register
7
SPIF WCOL OVR MODF 0
SPICSR 0
SOD SSM SSI
SOD bit SCK
Write SS
SPI STATE CONTROL
7
SPIE SPE
1 0
SPICR
0
SPR2 MSTR CPOL CPHA SPR1 SPR0
MASTER CONTROL SERIAL CLOCK GENERATOR SS
14.3.1
Functional description
A basic example of interconnections between a single master and a single slave is illustrated in Figure 56. The MOSI pins are connected together and the MISO pins are connected together. In this way data is transferred serially between master and slave (most significant bit first). The communication is always initiated by the master. When the master device transmits data to a slave device via MOSI pin, the slave device responds by sending data to the master device via the MISO pin. This implies full duplex communication with both data out and data in synchronized with the same clock signal (which is provided by the master device via the SCK pin). To use a single data line, the MISO and MOSI pins must be connected at each node (in this case only simplex communication is possible). Four possible data/clock timing relationships may be chosen (see Figure 59) but master and slave must be programmed with the same timing mode.
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Serial peripheral interface (SPI) Figure 56. Single master/single slave application
MASTER MSBit LSBit MISO MISO MSBit
ST72321Bxxx-Auto
SLAVE LSBit
8-BIT SHIFT REGISTER
8-BIT SHIFT REGISTER
MOSI
MOSI
SPI CLOCK GENERATOR
SCK SS +5V
SCK SS Not used if SS is managed by software
14.3.2
Slave select management
As an alternative to using the SS pin to control the Slave Select signal, the application can choose to manage the Slave Select signal by software. This is configured by the SSM bit in the SPICSR register (see Figure 58) In software management, the external SS pin is free for other application uses and the internal SS signal level is driven by writing to the SSI bit in the SPICSR register. In Master mode
SS internal must be held high continuously
In Slave mode There are two cases depending on the data/clock timing relationship (see Figure 57): If CPHA = 1 (data latched on 2nd clock edge):
SS internal must be held low during the entire transmission. This implies that in single slave applications the SS pin either can be tied to VSS, or made free for standard I/O by managing the SS function by software (SSM = 1 and SSI = 0 in the in the SPICSR register) SS internal must be held low during byte transmission and pulled high between each byte to allow the slave to write to the shift register. If SS is not pulled high, a Write Collision error will occur when the slave writes to the shift register (see Write collision error (WCOL) on page 133).
If CPHA = 0 (data latched on 1st clock edge):
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ST72321Bxxx-Auto Figure 57. Generic SS timing diagram
Serial peripheral interface (SPI)
MOSI/MISO
Byte 1
Byte 2
Byte 3
Master SS Slave SS (if CPHA=0)
Slave SS (if CPHA=1)
Figure 58. Hardware/Software slave select management
SSM bit
SSI bit SS external pin
1 0
SS internal
14.3.3
Master mode operation
In master mode, the serial clock is output on the SCK pin. The clock frequency, polarity and phase are configured by software (refer to the description of the SPICSR register).
Note:
The idle state of SCK must correspond to the polarity selected in the SPICSR register (by pulling up SCK if CPOL = 1 or pulling down SCK if CPOL = 0). How to operate the SPI in master mode To operate the SPI in master mode, perform the following steps in order: 1. Write to the SPICR register: a) b) Select the clock frequency by configuring the SPR[2:0] bits. Select the clock polarity and clock phase by configuring the CPOL and CPHA bits. Figure 59 shows the four possible configurations.
Note:
The slave must have the same CPOL and CPHA settings as the master. 2. Write to the SPICSR register: Either set the SSM bit and set the SSI bit or clear the SSM bit and tie the SS pin high for the complete byte transmit sequence. 3. Write to the SPICR register: Set the MSTR and SPE bits
Note:
MSTR and SPE bits remain set only if SS is high). IMPORTANT: If the SPICSR register is not written first, the SPICR register setting (MSTR bit) may not be taken into account. The transmit sequence begins when software writes a byte in the SPIDR register.
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Serial peripheral interface (SPI)
ST72321Bxxx-Auto
14.3.4
Master mode transmit sequence
When software writes to the SPIDR register, the data byte is loaded into the 8-bit shift register and then shifted out serially to the MOSI pin most significant bit first. When data transfer is complete: - - The SPIF bit is set by hardware An interrupt request is generated if the SPIE bit is set and the interrupt mask in the CCR register is cleared.
Clearing the SPIF bit is performed by the following software sequence: 1. 2. Note: An access to the SPICSR register while the SPIF bit is set A read to the SPIDR register.
While the SPIF bit is set, all writes to the SPIDR register are inhibited until the SPICSR register is read.
14.3.5
Slave mode operation
In slave mode, the serial clock is received on the SCK pin from the master device. To operate the SPI in slave mode: 1. Write to the SPICSR register to perform the following actions: a) Select the clock polarity and clock phase by configuring the CPOL and CPHA bits (see Figure 59). Manage the SS pin as described in Slave select management on page 128 and Figure 57. If CPHA = 1, SS must be held low continuously. If CPHA = 0, SS must be held low during byte transmission and pulled up between each byte to let the slave write in the shift register.
Note:
The slave must have the same CPOL and CPHA settings as the master. b)
2.
Write to the SPICR register to clear the MSTR bit and set the SPE bit to enable the SPI I/O functions.
14.3.6
Slave mode transmit sequence
When software writes to the SPIDR register, the data byte is loaded into the 8-bit shift register and then shifted out serially to the MISO pin most significant bit first. The transmit sequence begins when the slave device receives the clock signal and the most significant bit of the data on its MOSI pin. When data transfer is complete: - - The SPIF bit is set by hardware. An interrupt request is generated if SPIE bit is set and interrupt mask in the CCR register is cleared.
Clearing the SPIF bit is performed by the following software sequence: 1. 2. Note: An access to the SPICSR register while the SPIF bit is set A write or a read to the SPIDR register
While the SPIF bit is set, all writes to the SPIDR register are inhibited until the SPICSR register is read.
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ST72321Bxxx-Auto
Serial peripheral interface (SPI)
The SPIF bit can be cleared during a second transmission; however, it must be cleared before the second SPIF bit in order to prevent an Overrun condition (see Overrun condition (OVR) on page 133).
14.4
Clock phase and clock polarity
Four possible timing relationships may be chosen by software, using the CPOL and CPHA bits (see Figure 59).
Note:
The idle state of SCK must correspond to the polarity selected in the SPICSR register (by pulling up SCK if CPOL = 1 or pulling down SCK if CPOL = 0). The combination of the CPOL clock polarity and CPHA (clock phase) bits selects the data capture clock edge Figure 59 shows an SPI transfer with the four combinations of the CPHA and CPOL bits. The diagram may be interpreted as a master or slave timing diagram where the SCK pin, the MISO pin, the MOSI pin are directly connected between the master and the slave device.
Note:
If CPOL is changed at the communication byte boundaries, the SPI must be disabled by resetting the SPE bit.
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Serial peripheral interface (SPI) Figure 59. Data clock timing diagram
ST72321Bxxx-Auto
CPHA = 1
SCK (CPOL = 1)
SCK (CPOL = 0)
MISO (from master)
MSBit
Bit 6
Bit 5
Bit 4
Bit3
Bit 2
Bit 1
LSBit
MOSI (from slave)
MSBit
Bit 6
Bit 5
Bit 4
Bit3
Bit 2
Bit 1
LSBit
SS (to slave)
CAPTURE STROBE
CPHA = 0
SCK (CPOL = 1)
SCK (CPOL = 0)
MISO (from master)
MSBit
Bit 6
Bit 5
Bit 4
Bit3
Bit 2
Bit 1
LSBit
MOSI (from slave)
MSBit
Bit 6
Bit 5
Bit 4
Bit3
Bit 2
Bit 1
LSBit
SS (to slave)
CAPTURE STROBE
Note: This figure should not be used as a replacement for parametric information. Refer to Chapter 19: Electrical characteristics.
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ST72321Bxxx-Auto
Serial peripheral interface (SPI)
14.5
14.5.1
Error flags
Master mode fault (MODF)
Master mode fault occurs when the master device has its SS pin pulled low. When a Master mode fault occurs:

The MODF bit is set and an SPI interrupt request is generated if the SPIE bit is set. The SPE bit is reset. This blocks all output from the device and disables the SPI peripheral. The MSTR bit is reset, thus forcing the device into slave mode. A read access to the SPICSR register while the MODF bit is set. A write to the SPICR register.
Clearing the MODF bit is done through a software sequence: 1. 2. Note:
To avoid any conflicts in an application with multiple slaves, the SS pin must be pulled high during the MODF bit clearing sequence. The SPE and MSTR bits may be restored to their original state during or after this clearing sequence. Hardware does not allow the user to set the SPE and MSTR bits while the MODF bit is set except in the MODF bit clearing sequence.
14.5.2
Overrun condition (OVR)
An overrun condition occurs, when the master device has sent a data byte and the slave device has not cleared the SPIF bit issued from the previously transmitted byte. When an Overrun occurs:
The OVR bit is set and an interrupt request is generated if the SPIE bit is set.
In this case, the receiver buffer contains the byte sent after the SPIF bit was last cleared. A read to the SPIDR register returns this byte. All other bytes are lost. The OVR bit is cleared by reading the SPICSR register.
14.5.3
Write collision error (WCOL)
A write collision occurs when the software tries to write to the SPIDR register while a data transfer is taking place with an external device. When this happens, the transfer continues uninterrupted; and the software write will be unsuccessful. Write collisions can occur both in master and slave mode. See also Slave select management on page 128.
Note:
A "read collision" will never occur since the received data byte is placed in a buffer in which access is always synchronous with the MCU operation. The WCOL bit in the SPICSR register is set if a write collision occurs. No SPI interrupt is generated when the WCOL bit is set (the WCOL bit is a status flag only). Clearing the WCOL bit is done through a software sequence (see Figure 60).
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Figure 60. Clearing the WCOL bit (Write Collision Flag) software sequence
Clearing sequence after SPIF = 1 (end of a data byte transfer) 1st Step 2nd Step Read SPICSR RESULT SPIF = 0 WCOL = 0
Read SPIDR
Clearing sequence before SPIF = 1 (during a data byte transfer) 1st Step 2nd Step Read SPICSR RESULT Read SPIDR WCOL = 0
Note: Writing to the SPIDR register instead of reading it does not reset the WCOL bit.
14.5.4
Single master systems
A typical single master system may be configured, using an MCU as the master and four MCUs as slaves (see Figure 61). The master device selects the individual slave devices by using four pins of a parallel port to control the four SS pins of the slave devices. The SS pins are pulled high during reset since the master device ports will be forced to be inputs at that time, thus disabling the slave devices.
Note:
To prevent a bus conflict on the MISO line the master allows only one active slave device during a transmission. For more security, the slave device may respond to the master with the received data byte. Then the master will receive the previous byte back from the slave device if all MISO and MOSI pins are connected and the slave has not written to its SPIDR register. Other transmission security methods can use ports for handshake lines or data bytes with command fields. Figure 61. Single master / multiple slave configuration
SS SCK Slave MCU MOSI MISO SCK Slave MCU MOSI MISO SS SCK Slave MCU MOSI MISO SS SCK Slave MCU SS
MOSI
MISO
MOSI SCK Master MCU 5V SS
MISO
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Ports
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14.6
Low power modes
Table 63.
Mode Wait
Effect of low power modes on SPI
Effect No effect on SPI. SPI interrupt events cause the device to exit from Wait mode. SPI registers are frozen. In Halt mode, the SPI is inactive. SPI operation resumes when the MCU is woken up by an interrupt with "exit from Halt mode" capability. The data received is subsequently read from the SPIDR register when the software is running (interrupt vector fetching). If several data are received before the wake-up event, then an overrun error is generated. This error can be detected after the fetch of the interrupt routine that woke up the device.
Halt
14.6.1
Using the SPI to wake up the MCU from Halt mode
In slave configuration, the SPI is able to wake up the ST7 device from Halt mode through a SPIF interrupt. The data received is subsequently read from the SPIDR register when the software is running (interrupt vector fetch). If multiple data transfers have been performed before software clears the SPIF bit, then the OVR bit is set by hardware.
Note:
When waking up from Halt mode, if the SPI remains in Slave mode, it is recommended to perform an extra communications cycle to bring the SPI from Halt mode state to normal state. If the SPI exits from Slave mode, it returns to normal state immediately. The SPI can wake up the ST7 from Halt mode only if the Slave Select signal (external SS pin or the SSI bit in the SPICSR register) is low when the ST7 enters Halt mode. So if Slave selection is configured as external (see Slave select management on page 128), make sure the master drives a low level on the SS pin when the slave enters Halt mode.
Caution:
14.7
Interrupts
Table 64. SPI interrupt control/wake-up capability
Interrupt event SPI End of Transfer event Master Mode Fault event Overrun error Event flag SPIF MODF OVR SPIE Yes No Enable control bit Exit from Wait Exit from Halt Yes
Note:
The SPI interrupt events are connected to the same interrupt vector (see Interrupts chapter). They generate an interrupt if the corresponding Enable Control Bit is set and the interrupt mask in the CC register is reset (RIM instruction).
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14.8
14.8.1
SPI registers
Control register (SPICR)
SPICR 7 SPIE RW 6 SPE RW 5 SPR2 RW 4 MSTR RW 3 CPOL RW 2 CPHA RW Reset value: 0000 xxxx (0xh) 1 SPR[1:0] RW 0
Table 65.
Bit
SPICR register description
Function Serial Peripheral Interrupt Enable This bit is set and cleared by software. 0: Interrupt is inhibited 1: An SPI interrupt is generated whenever SPIF = 1, MODF = 1 or OVR = 1 in the SPICSR register. Serial Peripheral Output Enable This bit is set and cleared by software. It is also cleared by hardware when, in master mode, SS = 0 (see Master mode fault (MODF) on page 133). The SPE bit is cleared by reset, so the SPI peripheral is not initially connected to the external pins. 0: I/O pins free for general purpose I/O 1: SPI I/O pin alternate functions enabled Divider Enable This bit is set and cleared by software and is cleared by reset. It is used with the SPR[1:0] bits to set the baud rate. Refer to Table 66. 0: Divider by 2 enabled 1: Divider by 2 disabled Note: This bit has no effect in slave mode. Master Mode This bit is set and cleared by software. It is also cleared by hardware when, in master mode, SS = 0 (see Master mode fault (MODF) on page 133). 0: Slave mode 1: Master mode. The function of the SCK pin changes from an input to an output and the functions of the MISO and MOSI pins are reversed. Clock Polarity This bit is set and cleared by software. This bit determines the idle state of the serial Clock. The CPOL bit affects both the master and slave modes. 0: SCK pin has a low level idle state 1: SCK pin has a high level idle state Note: If CPOL is changed at the communication byte boundaries, the SPI must be disabled by resetting the SPE bit. Clock Phase This bit is set and cleared by software. 0: The first clock transition is the first data capture edge. 1: The second clock transition is the first capture edge. Note: The slave must have the same CPOL and CPHA settings as the master.
Name
7
SPIE
6
SPE
5
SPR2
4
MSTR
3
CPOL
2
CPHA
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Bit
Serial peripheral interface (SPI) SPICR register description (continued)
Function
Name
1:0
Serial Clock Frequency These bits are set and cleared by software. Used with the SPR2 bit, they select SPR[1:0] the baud rate of the SPI serial clock SCK output by the SPI in master mode. Note: These 2 bits have no effect in slave mode.
Table 66.
SPI master mode SCK frequency
Serial clock fCPU/4 fCPU/8 fCPU/16 fCPU/32 fCPU/64 fCPU/128 SPR2 1 0 0 1 0 0 SPR1 0 0 0 1 1 1 SPR0 0 0 1 0 0 1
14.8.2
Control/status register (SPICSR)
SPICSR 7 SPIF RO 6 WCOL RO 5 OVR RO 4 MODF RO 3 Reserved 2 SOD RW Reset value: 0000 0000 (00h) 1 SSM RW 0 SSI RW
Table 67.
Bit Name
SPICSR register description
Function Serial Peripheral Data Transfer Flag This bit is set by hardware when a transfer has been completed. An interrupt is generated if SPIE = 1 in the SPICR register. It is cleared by a software sequence (an access to the SPICSR register followed by a write or a read to the SPIDR register). 0: Data transfer is in progress or the flag has been cleared 1: Data transfer between the device and an external device has been completed. While the SPIF bit is set, all writes to the SPIDR register are inhibited until the SPICSR register is read.
7
SPIF
6
Write Collision status This bit is set by hardware when a write to the SPIDR register is done during a WCOL transmit sequence. It is cleared by a software sequence (see Figure 60). 0: No write collision occurred. 1: A write collision has been detected. SPI Overrun error This bit is set by hardware when the byte currently being received in the shift register is ready to be transferred into the SPIDR register while SPIF = 1 (see Overrun condition (OVR) on page 133). An interrupt is generated if SPIE = 1 in SPICR register. The OVR bit is cleared by software reading the SPICSR register. 0: No overrun error 1: Overrun error detected
5
OVR
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Serial peripheral interface (SPI) Table 67.
Bit Name
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SPICSR register description (continued)
Function
4
Mode Fault flag This bit is set by hardware when the SS pin is pulled low in master mode (see Master mode fault (MODF) on page 133). An SPI interrupt can be generated if SPIE = 1 in the SPICSR register. This bit is cleared by a software sequence (An MODF access to the SPICR register while MODF = 1 followed by a write to the SPICR register). 0: No master mode fault detected 1: A fault in master mode has been detected Reserved, must be kept cleared SPI Output Disable This bit is set and cleared by software. When set, it disables the alternate function of the SPI output (MOSI in master mode / MISO in slave mode). 0: SPI output enabled (if SPE = 1) 1: SPI output disabled SS Management This bit is set and cleared by software. When set, it disables the alternate function of the SPI SS pin and uses the SSI bit value instead. See Slave select management on page 128. 0: Hardware management (SS managed by external pin) 1: Software management (internal SS signal controlled by SSI bit. External SS pin free for general-purpose I/O) SS Internal Mode This bit is set and cleared by software. It acts as a `chip select' by controlling the level of the SS slave select signal when the SSM bit is set. 0: Slave selected 1: Slave deselected
3
2
SOD
1
SSM
0
SSI
14.8.3
Data I/O register (SPIDR)
SPIDR 7 6 5 4 D[7:0] RW 3 2 Reset value: Undefined 1 0
The SPIDR register is used to transmit and receive data on the serial bus. In a master device, a write to this register will initiate transmission/reception of another byte. Note: During the last clock cycle the SPIF bit is set, a copy of the received data byte in the shift register is moved to a buffer. When the user reads the serial peripheral data I/O register, the buffer is actually being read. While the SPIF bit is set, all writes to the SPIDR register are inhibited until the SPICSR register is read.
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Warning:
A write to the SPIDR register places data directly into the shift register for transmission.
A read to the SPIDR register returns the value located in the buffer and not the content of the shift register (see Figure 55). Table 68.
Address (Hex.) 0021h 0022h 0023h
SPI register map and reset values
Register label SPIDR Reset value SPICR Reset value SPICSR Reset value 7 MSB x SPIE 0 SPIF 0 6 5 4 3 2 1 0 LSB x SPR0 x SSI 0
x SPE 0 WCOL 0
x SPR2 0 OVR 0
x MSTR 0 MODF 0
x CPOL x 0
x CPHA x SOD 0
x SPR1 x SSM 0
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15
15.1
Serial communications interface (SCI)
Introduction
The Serial Communications Interface (SCI) offers a flexible means of full-duplex data exchange with external equipment requiring an industry standard NRZ asynchronous serial data format. The SCI offers a very wide range of baud rates using two baud rate generator systems.
15.2
Main features

Full duplex, asynchronous communications NRZ standard format (Mark/Space) Dual baud rate generator systems Independently programmable transmit and receive baud rates up to 500K baud Programmable data word length (8 or 9 bits) Receive buffer full, Transmit buffer empty and End of Transmission flags 2 receiver wake-up modes: - - Address bit (MSB) Idle line

Muting function for multiprocessor configurations Separate enable bits for Transmitter and Receiver 4 error detection flags: - - - - Overrun error Noise error Frame error Parity error Transmit data register empty Transmission complete Receive data register full Idle line received Overrun error detected Transmits parity bit Checks parity of received data byte
5 interrupt sources with flags: - - - - -
Parity control: - -
Reduced power consumption mode
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15.3
General description
The interface is externally connected to another device by two pins (see Figure 63):
TDO: Transmit Data Output. When the transmitter and the receiver are disabled, the output pin returns to its I/O port configuration. When the transmitter and/or the receiver are enabled and nothing is to be transmitted, the TDO pin is at high level. RDI: Receive Data Input is the serial data input. Oversampling techniques are used for data recovery by discriminating between valid incoming data and noise. An Idle Line prior to transmission or reception A start bit A data word (8 or 9 bits) least significant bit first A Stop bit indicating that the frame is complete A conventional type for commonly-used baud rates An extended type with a prescaler offering a very wide range of baud rates even with non-standard oscillator frequencies
Through these pins, serial data is transmitted and received as frames comprising:

This interface uses two types of baud rate generator:

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Serial communications interface (SCI) Figure 62. SCI block diagram
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Write
Read
(DATA REGISTER) DR
Transmit Data Register (TDR) TDO Transmit Shift Register RDI
Received Data Register (RDR)
Received Shift Register
CR1
R8 T8 SCID M WAKE PCE PS PIE
TRANSMIT CONTROL
WAKE UP UNIT
RECEIVER CONTROL
RECEIVER CLOCK
CR2
TIE TCIE RIE ILIE TE RE RWU SBK
TDRE TC RDRF IDLE OR NF FE PE
SR
SCI INTERRUPT CONTROL
TRANSMITTER CLOCK
TRANSMITTER RATE CONTROL fCPU /16 /PR
BRR
SCP1 SCP0 SCT2 SCT1 SCT0 SCR2 SCR1SCR0
RECEIVER RATE CONTROL
CONVENTIONAL BAUD RATE GENERATOR
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15.4
Functional description
The block diagram of the Serial Control Interface, is shown in Figure 62. It contains six dedicated registers:

2 control registers (SCICR1 and SCICR2) a status register (SCISR) a baud rate register (SCIBRR) an extended prescaler receiver register (SCIERPR) an extended prescaler transmitter register (SCIETPR)
Refer to the register descriptions in Section 15.7 for the definitions of each bit.
15.4.1
Serial data format
Word length may be selected as being either 8 or 9 bits by programming the M bit in the SCICR1 register (see Figure 62). The TDO pin is in low state during the start bit. The TDO pin is in high state during the stop bit. An Idle character is interpreted as an entire frame of `1's followed by the start bit of the next frame which contains data. A Break character is interpreted on receiving `0's for some multiple of the frame period. At the end of the last break frame the transmitter inserts an extra `1' bit to acknowledge the start bit. Transmission and reception are driven by their own baud rate generator.
Figure 63. Word length programming
9-bit Word length (M bit is set) Data Frame
Start Bit Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 Possible Parity Bit Bit8 Stop Bit
Next Data Frame
Next Start Bit
Idle Frame
Start Bit
Break Frame
Extra `1'
Start Bit
8-bit Word length (M bit is reset) Data Frame
Start Bit Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6
Possible Parity Bit Bit7 Stop Bit
Next Data Frame
Next Start Bit
Idle Frame
Start Bit
Break Frame
Extra `1'
Start Bit
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15.4.2
Transmitter
The transmitter can send data words of either 8 or 9 bits depending on the M bit status. When the M bit is set, word length is 9 bits and the 9th bit (the MSB) has to be stored in the T8 bit in the SCICR1 register.
Character transmission
During an SCI transmission, data shifts out least significant bit first on the TDO pin. In this mode, the SCIDR register consists of a buffer (TDR) between the internal bus and the transmit shift register (see Figure 62). Procedure 1. 2. 3. 4. Select the M bit to define the word length. Select the desired baud rate using the SCIBRR and the SCIETPR registers. Set the TE bit to assign the TDO pin to the alternate function and to send an idle frame as first transmission. Access the SCISR register and write the data to send in the SCIDR register (this sequence clears the TDRE bit). Repeat this sequence for each data to be transmitted. An access to the SCISR register A write to the SCIDR register The TDR register is empty. The data transfer is beginning. The next data can be written in the SCIDR register without overwriting the previous data.
Clearing the TDRE bit is always performed by the following software sequence: 1. 2.

The TDRE bit is set by hardware and it indicates:
This flag generates an interrupt if the TIE bit is set and the I bit is cleared in the CCR register. When a transmission is taking place, a write instruction to the SCIDR register stores the data in the TDR register and which is copied in the shift register at the end of the current transmission. When no transmission is taking place, a write instruction to the SCIDR register places the data directly in the shift register, the data transmission starts, and the TDRE bit is immediately set. When a frame transmission is complete (after the stop bit) the TC bit is set and an interrupt is generated if the TCIE is set and the I bit is cleared in the CCR register. Clearing the TC bit is performed by the following software sequence: 1. 2. Note: An access to the SCISR register A write to the SCIDR register
The TDRE and TC bits are cleared by the same software sequence. Break characters Setting the SBK bit loads the shift register with a break character. The break frame length depends on the M bit (see Figure 63). As long as the SBK bit is set, the SCI send break frames to the TDO pin. After clearing this
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bit by software the SCI insert a logic 1 bit at the end of the last break frame to guarantee the recognition of the start bit of the next frame. Idle characters Setting the TE bit drives the SCI to send an idle frame before the first data frame. Clearing and then setting the TE bit during a transmission sends an idle frame after the current word. Note: Resetting and setting the TE bit causes the data in the TDR register to be lost. Therefore the best time to toggle the TE bit is when the TDRE bit is set, that is, before writing the next byte in the SCIDR.
15.4.3
Receiver
The SCI can receive data words of either 8 or 9 bits. When the M bit is set, word length is 9 bits and the MSB is stored in the R8 bit in the SCICR1 register.
Character reception
During a SCI reception, data shifts in least significant bit first through the RDI pin. In this mode, the SCIDR register consists or a buffer (RDR) between the internal bus and the received shift register (see Figure 62). Procedure 1. 2. 3.

Select the M bit to define the word length. Select the desired baud rate using the SCIBRR and the SCIERPR registers. Set the RE bit, this enables the receiver which begins searching for a start bit. The RDRF bit is set. It indicates that the content of the shift register is transferred to the RDR. An interrupt is generated if the RIE bit is set and the I bit is cleared in the CCR register. The error flags can be set if a frame error, noise or an overrun error has been detected during reception. An access to the SCISR register A read to the SCIDR register.
When a character is received:
Clearing the RDRF bit is performed by the following software sequence done by: 1. 2.
The RDRF bit must be cleared before the end of the reception of the next character to avoid an overrun error. Break character When a break character is received, the SCI handles it as a framing error. Idle character When an idle frame is detected, there is the same procedure as a data received character plus an interrupt if the ILIE bit is set and the I bit is cleared in the CCR register. Overrun error An overrun error occurs when a character is received when RDRF has not been reset. Data cannot be transferred from the shift register to the RDR register as long as the RDRF bit is not cleared.
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Serial communications interface (SCI) When an overrun error occurs:

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The OR bit is set. The RDR content is not lost. The shift register is overwritten. An interrupt is generated if the RIE bit is set and the I bit is cleared in the CCR register.
The OR bit is reset by an access to the SCISR register followed by a SCIDR register read operation. Noise error Oversampling techniques are used for data recovery by discriminating between valid incoming data and noise. Normal data bits are considered valid if three consecutive samples (8th, 9th, 10th) have the same bit value, otherwise the NF flag is set. In the case of start bit detection, the NF flag is set on the basis of an algorithm combining both valid edge detection and three samples (8th, 9th, 10th). Therefore, to prevent the NF flag getting set during start bit reception, there should be a valid edge detection as well as three valid samples. When noise is detected in a frame:

The NF flag is set at the rising edge of the RDRF bit. Data is transferred from the Shift register to the SCIDR register. No interrupt is generated. However this bit rises at the same time as the RDRF bit which itself generates an interrupt.
The NF flag is reset by a SCISR register read operation followed by a SCIDR register read operation. During reception, if a false start bit is detected (for example, 8th, 9th, 10th samples are 011, 101, 110), the frame is discarded and the receiving sequence is not started for this frame. There is no RDRF bit set for this frame and the NF flag is set internally (not accessible to the user). This NF flag is accessible along with the RDRF bit when a next valid frame is received. Note: If the application Start Bit is not long enough to match the above requirements, then the NF Flag may get set due to the short Start Bit. In this case, the NF flag may be ignored by the application software when the first valid byte is received. See also Noise error causes on page 150.
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Figure 64. SCI baud rate and extended prescaler block diagram
TRANSMITTER CLOCK EXTENDED PRESCALER TRANSMITTER RATE CONTROL
SCIETPR EXTENDED TRANSMITTER PRESCALER REGISTER SCIERPR EXTENDED RECEIVER PRESCALER REGISTER RECEIVER CLOCK EXTENDED PRESCALER RECEIVER RATE CONTROL EXTENDED PRESCALER
fCPU
TRANSMITTER RATE CONTROL /16 /PR SCIBRR SCP1 SCP0 SCT2 SCT1 SCT0 SCR2 SCR1 SCR0
RECEIVER RATE CONTROL
CONVENTIONAL BAUD RATE GENERATOR
Framing error A framing error is detected when:

The stop bit is not recognized on reception at the expected time, following either a desynchronization or excessive noise. A break is received. The FE bit is set by hardware. Data is transferred from the Shift register to the SCIDR register. No interrupt is generated. However this bit rises at the same time as the RDRF bit which itself generates an interrupt.
When the framing error is detected:

The FE bit is reset by a SCISR register read operation followed by a SCIDR register read operation.
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Conventional baud rate generation
The baud rate for the receiver and transmitter (Rx and Tx) are set independently and calculated as follows: fCPU fCPU Rx = Tx = (16*PR)*RR (16*PR)*TR with: PR = 1, 3, 4 or 13 (see SCP[1:0] bits) TR = 1, 2, 4, 8, 16, 32, 64,128 (see SCT[2:0] bits) RR = 1, 2, 4, 8, 16, 32, 64,128 (see SCR[2:0] bits) All these bits are in the SCIBRR register. Example: If fCPU is 8 MHz (normal mode) and if PR = 13 and TR = RR = 1, the transmit and receive baud rates are 38400 baud. Note: The baud rate registers MUST NOT be changed while the transmitter or the receiver is enabled.
Extended baud rate generation
The extended prescaler option provides a very fine tuning of the baud rate, using a 255 value prescaler, whereas the conventional baud rate generator retains industry standard software compatibility. The extended baud rate generator block diagram is described in the Figure 64. The output clock rate sent to the transmitter or to the receiver is the output from the 16 divider divided by a factor ranging from 1 to 255 set in the SCIERPR or the SCIETPR register. Note: The extended prescaler is activated by setting the SCIETPR or SCIERPR register to a value other than zero. The baud rates are calculated as follows: fCPU fCPU Rx = Tx = 16*ERPR*(PR*RR) 16*ETPR*(PR*TR) with: ETPR = 1,..,255 (see SCIETPR register) ERPR = 1,..,255 (see SCIERPR register)
Receiver muting and wake-up feature
In multiprocessor configurations it is often desirable that only the intended message recipient should actively receive the full message contents, thus reducing redundant SCI service overhead for all non-addressed receivers. The non-addressed devices may be placed in sleep mode by means of the muting function. Setting the RWU bit by software puts the SCI in sleep mode:

All the reception status bits cannot be set. All the receive interrupts are inhibited. by Idle Line detection if the WAKE bit is reset by Address Mark detection if the WAKE bit is set
A muted receiver may be awakened by one of the following two ways:

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A receiver wakes up by Idle Line detection when the Receive line has recognized an Idle Frame. Then the RWU bit is reset by hardware but the IDLE bit is not set. Receiver wakes up by Address Mark detection when it received a `1' as the most significant bit of a word, thus indicating that the message is an address. The reception of this particular word wakes up the receiver, resets the RWU bit and sets the RDRF bit, which allows the receiver to receive this word normally and to use it as an address word. Caution: In Mute mode, do not write to the SCICR2 register. If the SCI is in Mute mode during the read operation (RWU = 1) and a address mark wake-up event occurs (RWU is reset) before the write operation, the RWU bit is set again by this write operation. Consequently the address byte is lost and the SCI is not woken up from Mute mode.
Parity control
Parity control (generation of parity bit in transmission and parity checking in reception) can be enabled by setting the PCE bit in the SCICR1 register. Depending on the frame length defined by the M bit, the possible SCI frame formats are as listed in Table 69. Table 69.
M bit 0 0 1 1
Frame formats
PCE bit 0 1 0 1 SCI frame | SB | 8 bit data | STB | | SB | 7-bit data | PB | STB | | SB | 9-bit data | STB | | SB | 8-bit data PB | STB |
Legend: SB = Start Bit, STB = Stop Bit, PB = Parity Bit Note: In case of wake-up by an address mark, the MSB bit of the data is taken into account and not the parity bit Even parity: the parity bit is calculated to obtain an even number of `1's inside the frame made of the 7 or 8 LSB bits (depending on whether M is equal to 0 or 1) and the parity bit. Example: data = 00110101; 4 bits set => parity bit is 0 if even parity is selected (PS bit = 0). Odd parity: the parity bit is calculated to obtain an odd number of `1's inside the frame made of the 7 or 8 LSB bits (depending on whether M is equal to 0 or 1) and the parity bit. Example: data = 00110101; 4 bits set => parity bit is 1 if odd parity is selected (PS bit = 1). Transmission mode: If the PCE bit is set then the MSB bit of the data written in the data register is not transmitted but is changed by the parity bit. Reception mode: If the PCE bit is set then the interface checks if the received data byte has an even number of `1's if even parity is selected (PS = 0) or an odd number of `1's if odd parity is selected (PS = 1). If the parity check fails, the PE flag is set in the SCISR register and an interrupt is generated if PIE is set in the SCICR1 register.
SCI clock tolerance
During reception, each bit is sampled 16 times. The majority of the 8th, 9th and 10th samples is considered as the bit value. For a valid bit detection, all the three samples should have the same value otherwise the noise flag (NF) is set. For example: If the 8th, 9th and 10th samples are 0, 1 and 1 respectively, then the bit value is `1', but the Noise Flag bit is set because the three samples values are not the same.
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Consequently, the bit length must be long enough so that the 8th, 9th and 10th samples have the desired bit value. This means the clock frequency should not vary more than 6/16 (37.5%) within one bit. The sampling clock is resynchronized at each start bit, so that when receiving 10 bits (one start bit, 1 data byte, 1 stop bit), the clock deviation must not exceed 3.75%. Note: The internal sampling clock of the microcontroller samples the pin value on every falling edge. Therefore, the internal sampling clock and the time the application expects the sampling to take place may be out of sync. For example: If the baud rate is 15.625 Kbaud (bit length is 64s), then the 8th, 9th and 10th samples are at 28s, 32s and 36s respectively (the first sample starting ideally at 0s). But if the falling edge of the internal clock occurs just before the pin value changes, the samples would then be out of sync by ~4us. This means the entire bit length must be at least 40s (36s for the 10th sample + 4s for synchronization with the internal sampling clock).
Clock deviation causes
The causes which contribute to the total deviation are: - - - DTRA: Deviation due to transmitter error (Local oscillator error of the transmitter or the transmitter is transmitting at a different baud rate). DQUANT: Error due to the baud rate quantization of the receiver. DREC: Deviation of the local oscillator of the receiver: This deviation can occur during the reception of one complete SCI message assuming that the deviation has been compensated at the beginning of the message. DTCL: Deviation due to the transmission line (generally due to the transceivers) DTRA + DQUANT + DREC + DTCL < 3.75%
-
All the deviations of the system should be added and compared to the SCI clock tolerance:
Noise error causes
See also description of noise error in Receiver on page 145. Start bit The noise flag (NF) is set during start bit reception if one of the following conditions occurs: 1. A valid falling edge is not detected. A falling edge is considered to be valid if the 3 consecutive samples before the falling edge occurs are detected as `1' and, after the falling edge occurs, during the sampling of the 16 samples, if one of the samples numbered 3, 5 or 7 is detected as a `1'. During sampling of the 16 samples, if one of the samples numbered 8, 9 or 10 is detected as a `1'.
2.
Therefore, a valid Start Bit must satisfy both the above conditions to prevent the Noise Flag getting set. Data bits The noise flag (NF) is set during normal data bit reception if the following condition occurs:
During the sampling of 16 samples, if all three samples numbered 8, 9 and10 are not the same. The majority of the 8th, 9th and 10th samples is considered as the bit value.
Therefore, a valid Data Bit must have samples 8, 9 and 10 at the same value to prevent the Noise Flag from getting set.
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ST72321Bxxx-Auto Figure 65. Bit sampling in reception mode
Serial communications interface (SCI)
RDI LINE sampled values Sample clock
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
6/16 7/16 One bit time 7/16
15.5
Low power modes
Table 70.
Mode Wait Halt
Effect of low power modes on SCI
Effect No effect on SCI. SCI interrupts cause the device to exit from Wait mode. SCI registers are frozen. In Halt mode, the SCI stops transmitting/receiving until Halt mode is exited.
15.6
Interrupts
The SCI interrupt events are connected to the same interrupt vector. These events generate an interrupt if the corresponding Enable Control Bit is set and the interrupt mask in the CC register is reset (RIM instruction). Table 71. SCI interrupt control/wake-up capability
Event flag TDRE TC RDRF RIE Overrun Error Detected OR Yes No Enable control bit TIE TCIE Exit from Wait Yes Yes Yes Exit from Halt No No No
Interrupt event Transmit Data Register Empty Transmission Complete Received Data Ready to be Read
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Serial communications interface (SCI) Table 71. SCI interrupt control/wake-up capability
Event flag IDLE PE Enable control bit ILIE PIE
ST72321Bxxx-Auto
Interrupt event Idle Line Detected Parity Error
Exit from Wait Yes Yes
Exit from Halt No No
15.7
15.7.1
SCI registers
Status register (SCISR)
SCISR 7 TDRE RO 6 TC RO 5 RDRF RO 4 IDLE RO 3 OR RO 2 NF RO Reset value: 1100 0000 (C0h) 1 FE RO 0 PE RO
Table 72.
Bit Name
SCISR register description
Function
7
Transmit data register empty This bit is set by hardware when the content of the TDR register has been transferred into the shift register. An interrupt is generated if the TIE bit = 1 in the SCICR2 register. It is cleared by a software sequence (an access to the SCISR TDRE register followed by a write to the SCIDR register). 0: Data is not transferred to the shift register 1: Data is transferred to the shift register Note: Data is not transferred to the shift register unless the TDRE bit is cleared. Transmission complete This bit is set by hardware when transmission of a frame containing Data is complete. An interrupt is generated if TCIE = 1 in the SCICR2 register. It is cleared by a software sequence (an access to the SCISR register followed by a write to the SCIDR register). 0: Transmission is not complete 1: Transmission is complete Note: TC is not set after the transmission of a Preamble or a Break.
6
TC
5
Received data ready flag This bit is set by hardware when the content of the RDR register has been transferred to the SCIDR register. An interrupt is generated if RIE = 1 in the SCICR2 RDRF register. It is cleared by a software sequence (an access to the SCISR register followed by a read to the SCIDR register). 0: Data is not received 1: Received data is ready to be read
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ST72321Bxxx-Auto Table 72.
Bit Name
Serial communications interface (SCI) SCISR register description (continued)
Function Idle line detect This bit is set by hardware when an Idle Line is detected. An interrupt is generated if the ILIE = 1 in the SCICR2 register. It is cleared by a software sequence (an access to the SCISR register followed by a read to the SCIDR register). 0: No Idle Line is detected 1: Idle Line is detected Note: The IDLE bit is not set again until the RDRF bit has been set itself (that is, a new idle line occurs). Overrun error This bit is set by hardware when the word currently being received in the shift register is ready to be transferred into the RDR register while RDRF = 1. An interrupt is generated if RIE = 1 in the SCICR2 register. It is cleared by a software sequence (an access to the SCISR register followed by a read to the SCIDR register). 0: No Overrun error 1: Overrun error is detected Note: When this bit is set RDR register content is not lost but the shift register is overwritten. Noise flag This bit is set by hardware when noise is detected on a received frame. It is cleared by a software sequence (an access to the SCISR register followed by a read to the SCIDR register). 0: No noise is detected 1: Noise is detected Note: This bit does not generate interrupt as it appears at the same time as the RDRF bit which itself generates an interrupt. Framing error This bit is set by hardware when a de-synchronization, excessive noise or a break character is detected. It is cleared by a software sequence (an access to the SCISR register followed by a read to the SCIDR register). 0: No Framing error is detected 1: Framing error or break character is detected Note: This bit does not generate interrupt as it appears at the same time as the RDRF bit which itself generates an interrupt. If the word currently being transferred causes both frame error and overrun error, it will be transferred and only the OR bit will be set. Parity error This bit is set by hardware when a parity error occurs in receiver mode. It is cleared by a software sequence (a read to the status register followed by an access to the SCIDR data register). An interrupt is generated if PIE = 1 in the SCICR1 register. 0: No parity error 1: Parity error
4
IDLE
3
OR
2
NF
1
FE
0
PE
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Serial communications interface (SCI)
ST72321Bxxx-Auto
15.7.2
Control register 1 (SCICR1)
SCICR1 7 R8 RW 6 T8 RW 5 SCID RW 4 M RW 3 WAKE RW 2 PCE RW Reset value: X000 0000 (x0h) 1 PS RW 0 PIE RW
Table 73.
Bit 7 6 Name R8 T8
SCICR1 register description
Function Receive data bit 8 This bit is used to store the 9th bit of the received word when M = 1. Transmit data bit 8 This bit is used to store the 9th bit of the transmitted word when M = 1. Disabled for low power consumption When this bit is set the SCI prescalers and outputs are stopped and the end of the current byte transfer in order to reduce power consumption.This bit is set and cleared by software. 0: SCI enabled 1: SCI prescaler and outputs disabled Word length This bit determines the word length. It is set or cleared by software. 0: 1 Start bit, 8 Data bits, 1 Stop bit 1: 1 Start bit, 9 Data bits, 1 Stop bit Note: The M bit must not be modified during a data transfer (both transmission and reception).
5
SCID
4
M
3
Wake-up method This bit determines the SCI wake-up method. It is set or cleared by software. WAKE 0: Idle line 1: Address mark Parity control enable This bit selects the hardware parity control (generation and detection). When the parity control is enabled, the computed parity is inserted at the MSB position (9th bit if M = 1; 8th bit if M = 0) and parity is checked on the received data. This bit is set and cleared by software. Once it is set, PCE is active after the current byte (in reception and in transmission). 0: Parity control disabled 1: Parity control enabled Parity selection This bit selects the odd or even parity when the parity generation/detection is enabled (PCE bit set). It is set and cleared by software. The parity is selected after the current byte. 0: Even parity 1: Odd parity
2
PCE
1
PS
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ST72321Bxxx-Auto Table 73.
Bit Name
Serial communications interface (SCI) SCICR1 register description (continued)
Function Parity interrupt enable This bit enables the interrupt capability of the hardware parity control when a parity error is detected (PE bit set). It is set and cleared by software. 0: Parity error interrupt disabled 1: Parity error interrupt enabled
0
PIE
15.7.3
Control register 2 (SCICR2)
SCICR2 7 TIE RW 6 TCIE RW 5 RIE RW 4 ILIE RW 3 TE RW 2 RE RW Reset value: 0000 0000 (00h) 1 RWU RW 0 SBK RW
Table 74.
Bit Name
SCICR2 register description
Function Transmitter interrupt enable This bit is set and cleared by software. 0: Interrupt is inhibited 1: An SCI interrupt is generated whenever TDRE = 1 in the SCISR register.
7
TIE
6
Transmission complete interrupt enable This bit is set and cleared by software. TCIE 0: Interrupt is inhibited 1: An SCI interrupt is generated whenever TC = 1 in the SCISR register. Receiver interrupt enable This bit is set and cleared by software. 0: Interrupt is inhibited 1: An SCI interrupt is generated whenever OR = 1 or RDRF = 1 in the SCISR register. Idle line interrupt enable This bit is set and cleared by software. 0: Interrupt is inhibited 1: An SCI interrupt is generated whenever IDLE = 1 in the SCISR register. Transmitter enable This bit enables the transmitter. It is set and cleared by software. 0: Transmitter is disabled 1: Transmitter is enabled Notes: During transmission, a `0' pulse on the TE bit (`0' followed by `1') sends a preamble (idle line) after the current word. When TE is set there is a 1 bit-time delay before the transmission starts. Caution: The TDO pin is free for general purpose I/O only when the TE and RE bits are both cleared (or if TE is never set).
5
RIE
4
ILIE
3
TE
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Serial communications interface (SCI) Table 74.
Bit Name
ST72321Bxxx-Auto
SCICR2 register description (continued)
Function Receiver enable This bit enables the receiver. It is set and cleared by software. 0: Receiver is disabled 1: Receiver is enabled and begins searching for a start bit
2
RE
1
Receiver wake-up This bit determines if the SCI is in mute mode or not. It is set and cleared by software and can be cleared by hardware when a wake-up sequence is recognized. 0: Receiver in Active mode RWU 1: Receiver in Mute mode Note: Before selecting Mute mode (setting the RWU bit), the SCI must receive some data first, otherwise it cannot function in Mute mode with wake-up by idle line detection. Send break This bit set is used to send break characters. It is set and cleared by software. 0: No break character is transmitted 1: Break characters are transmitted Note: If the SBK bit is set to `1' and then to `0', the transmitter sends a BREAK word at the end of the current word.
0
SBK
15.7.4
Data register (SCIDR)
This register contains the Received or Transmitted data character, depending on whether it is read from or written to.
SCIDR 7 6 5 4 DR[7:0] RW 3 2 Reset value: Undefined 1 0
The Data register performs a double function (read and write) since it is composed of two registers, one for transmission (TDR) and one for reception (RDR). The TDR register provides the parallel interface between the internal bus and the output shift register (see Figure 62). The RDR register provides the parallel interface between the input shift register and the internal bus (see Figure 62).
15.7.5
Baud rate register (SCIBRR)
SCIBRR 7 SCP[1:0] RW 6 5 4 SCT[2:0] RW 3 2 Reset value: 0000 0000 (00h) 1 SCR[2:0] RW 0
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ST72321Bxxx-Auto Table 75.
Bit Name
Serial communications interface (SCI) SCIBRR register description
Function
First SCI Prescaler These 2 prescaling bits allow several standard clock division ranges. 00: PR prescaling factor = 1 7:6 SCP[1:0] 01: PR prescaling factor = 3 10: PR prescaling factor = 4 11: PR prescaling factor = 13 SCI Transmitter rate divisor These 3 bits, in conjunction with the SCP1 and SCP0 bits define the total division applied to the bus clock to yield the transmit rate clock in conventional Baud Rate Generator mode. 000: TR dividing factor = 1 001: TR dividing factor = 2 5:3 SCT[2:0] 010: TR dividing factor = 4 011: TR dividing factor = 8 100: TR dividing factor = 16 101: TR dividing factor = 32 110: TR dividing factor = 64 111: TR dividing factor = 128 SCI Receiver rate divisor These 3 bits, in conjunction with the SCP[1:0] bits define the total division applied to the bus clock to yield the receive rate clock in conventional Baud Rate Generator mode. 000: RR dividing factor = 1 001: RR dividing factor = 2 2:0 SCR[2:0] 010: RR dividing factor = 4 011: RR dividing factor = 8 100: RR dividing factor = 16 101: RR dividing factor = 32 110: RR dividing factor = 64 111: RR dividing factor = 128
15.7.6
Extended receive prescaler division register (SCIERPR)
This register allows setting of the extended prescaler rate division factor for the receive circuit.
SCIERPR 7 6 5 4 ERPR[7:0] RW 3 2 Reset value: 0000 0000 (00h) 1 0
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Serial communications interface (SCI) Table 76.
Bit
ST72321Bxxx-Auto
SCIERPR register description
Function
Name
8-bit Extended Receive Prescaler Register The extended baud rate generator is activated when a value different from 00h is stored in this register. Therefore the clock frequency issued from the 16 divider 7:0 ERPR[7:0] (see Figure 64) is divided by the binary factor set in the SCIERPR register (in the range 1 to 255). The extended baud rate generator is not used after a reset.
15.7.7
Extended transmit prescaler division register (SCIETPR)
This register allows setting of the external prescaler rate division factor for the transmit circuit.
SCIETPR 7 6 5 4 ETPR[7:0] RW 3 2 Reset value: 0000 0000 (00h) 1 0
Table 77.
Bit
SCIETPR register description
Function
Name
8-bit Extended Transmit Prescaler Register The extended baud rate generator is activated when a value different from 00h is stored in this register. Therefore the clock frequency issued from the 16 divider 7:0 ETPR[7:0] (see Figure 64) is divided by the binary factor set in the SCIETPR register (in the range 1 to 255). The extended baud rate generator is not used after a reset.
Table 78.
Baud rate selection
Conditions
Symbol
Parameter fCPU
Accuracy versus standard
Standard Prescaler Conventional mode TR (or RR) = 128, PR = 13 TR (or RR) = 32, PR = 13 TR (or RR) = 16, PR = 13 TR (or RR) = 8, PR = 13 TR (or RR) = 4, PR = 13 TR (or RR) = 16, PR = 3 TR (or RR) = 2, PR = 13 TR (or RR) = 1, PR = 13 Extended mode ETPR (or ERPR) = 35, TR (or RR) = 1, PR = 1
Baud rate
Unit
~0.16% fTx fRx Communication frequency 8 MHz
300 1200 2400 4800 9600 10400 19200 38400
~300.48 ~1201.92 ~2403.84 ~4807.69 ~9615.38 ~10416.67 ~19230.77 ~38461.54
Hz
~0.79%
14400
~14285.71
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ST72321Bxxx-Auto Table 79. SCI register map and reset values
7 TDRE 1 MSB x SCP1 0 R8 x TIE 0 MSB 0 MSB 0 6 TC 1 x SCP0 0 T8 0 TCIE 0 0 0 5 RDRF 0 x SCT2 0 SCID 0 RIE 0 0 0 4
Serial communications interface (SCI)
Address (Hex.) Register label 0050h 0051h 0052h 0053h 0054h 0055h 0057h SCISR Reset value SCIDR Reset value SCIBRR Reset value SCICR1 Reset value SCICR2 Reset value SCIERPR Reset value SCIPETPR Reset value
3 OR 0 x SCT0 0 WAKE 0 TE 0 0 0
2 NF 0 x SCR2 0 PCE 0 RE 0 0 0
1 FE 0 x SCR1 0 PS 0 RWU 0 0 0
0 PE 0 LSB x SCR0 0 PIE 0 SBK 0 LSB 0 LSB 0
IDLE 0 x SCT1 0 M 0 ILIE 0 0 0
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I2C bus interface (I2C)
ST72321Bxxx-Auto
16
16.1
I2C bus interface (I2C)
Introduction
The I2C bus interface serves as an interface between the microcontroller and the serial I2C bus. It provides both multimaster and slave functions, and controls all I2C bus-specific sequencing, protocol, arbitration and timing. It supports fast I2C mode (400 kHz).
16.2
Main features

Parallel-bus/I2C protocol converter Multimaster capability 7-bit/10-bit addressing SMBus V1.1 compliant Transmitter/Receiver flag End-of-byte transmission flag Transfer problem detection
16.2.1
I2C master features

Clock generation I2C bus busy flag Arbitration Lost flag End of byte transmission flag Transmitter/Receiver flag Start bit detection flag Start and Stop generation
16.2.2
I2C slave features

Stop bit detection I2C bus busy flag Detection of misplaced start or stop condition Programmable I2C address detection Transfer problem detection End-of-byte transmission flag Transmitter/Receiver flag
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ST72321Bxxx-Auto
I2C bus interface (I2C)
16.3
General description
In addition to receiving and transmitting data, this interface converts it from serial to parallel format and vice versa, using either an interrupt or polled handshake. The interrupts are enabled or disabled by software. The interface is connected to the I2C bus by a data pin (SDAI) and by a clock pin (SCLI). It can be connected both with a standard I2C bus and a fast I2C bus. This selection is made by software.
16.3.1
Mode selection
The interface can operate in the four following modes:

Slave transmitter/receiver Master transmitter/receiver
By default, it operates in slave mode. The interface automatically switches from slave to master after it generates a START condition and from master to slave in case of arbitration loss or a STOP generation, allowing then Multimaster capability.
16.3.2
Communication flow
In Master mode, it initiates a data transfer and generates the clock signal. A serial data transfer always begins with a start condition and ends with a stop condition. Both start and stop conditions are generated in master mode by software. In Slave mode, the interface is capable of recognizing its own address (7- or 10-bit), and the General Call address. The General Call address detection may be enabled or disabled by software. Data and addresses are transferred as 8-bit bytes, MSB first. The first byte(s) following the start condition contain the address (one in 7-bit mode, two in 10-bit mode). The address is always transmitted in Master mode. A 9th clock pulse follows the 8 clock cycles of a byte transfer, during which the receiver must send an acknowledge bit to the transmitter. Refer to Figure 66. Figure 66. I2C bus protocol
SDA MSB SCL 1 START CONDITION 2 8 9 STOP CONDITION
ACK
VR02119B
Acknowledge may be enabled and disabled by software. The I2C interface address and/or general call address can be selected by software. The speed of the I2C interface may be selected between standard (up to 100 kHz) and fast I2C (up to 400 kHz).
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I2C bus interface (I2C)
ST72321Bxxx-Auto
16.3.3
SDA/SCL line control
Transmitter mode
The interface holds the clock line low before transmission to wait for the microcontroller to write the byte in the data register.
Receiver mode
The interface holds the clock line low after reception to wait for the microcontroller to read the byte in the data register. The SCL frequency (fSCL) is controlled by a programmable clock divider which depends on the I2C bus mode. When the I2C cell is enabled, the SDA and SCL ports must be configured as floating inputs. In this case, the value of the external pull-up resistor used depends on the application. When the I2C cell is disabled, the SDA and SCL ports revert to being standard I/O port pins. Figure 67. I2C interface block diagram
DATA REGISTER (DR)
SDA or SDAI
DATA CONTROL DATA SHIFT REGISTER
COMPARATOR
OWN ADDRESS REGISTER 1 (OAR1) OWN ADDRESS REGISTER 2 (OAR2)
SCL or SCLI
CLOCK CONTROL
CLOCK CONTROL REGISTER (CCR)
CONTROL REGISTER (CR) STATUS REGISTER 1 (SR1) STATUS REGISTER 2 (SR2) CONTROL LOGIC
INTERRUPT
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ST72321Bxxx-Auto
I2C bus interface (I2C)
16.4
Functional description
Refer to the CR, SR1 and SR2 registers in Section 16.7 for the bit definitions. By default the I2C interface operates in Slave mode (M/SL bit is cleared) except when it initiates a transmit or receive sequence. First the interface frequency must be configured using the FRi bits in the OAR2 register.
16.4.1
Slave mode
As soon as a start condition is detected, the address is received from the SDA line and sent to the shift register; then it is compared with the address of the interface or the General Call address (if selected by software).
Note:
In 10-bit addressing mode, the comparison includes the header sequence (11110xx0) and the two most significant bits of the address. Header matched (10-bit mode only): The interface generates an acknowledge pulse if the ACK bit is set. Address not matched: The interface ignores it and waits for another Start condition. Address matched: The interface generates in sequence:

an acknowledge pulse if the ACK bit is set EVF and ADSL bits are set with an interrupt if the ITE bit is set.
Then the interface waits for a read of the SR1 register, holding the SCL line low (see Figure 68: Transfer sequencing EV1). Next, in 7-bit mode read the DR register to determine from the least significant bit (Data Direction Bit) if the slave must enter Receiver or Transmitter mode. In 10-bit mode, after receiving the address sequence the slave is always in receive mode. It will enter transmit mode on receiving a repeated Start condition followed by the header sequence with matching address bits and the least significant bit set (11110xx1).
Slave receiver
Following the address reception and after the SR1 register has been read, the slave receives bytes from the SDA line into the DR register via the internal shift register. After each byte the interface generates in sequence:

an acknowledge pulse if the ACK bit is set EVF and BTF bits are set with an interrupt if the ITE bit is set.
Then the interface waits for a read of the SR1 register followed by a read of the DR register, holding the SCL line low (see Figure 68: Transfer sequencing EV2).
Slave transmitter
Following the address reception and after SR1 register has been read, the slave sends bytes from the DR register to the SDA line via the internal shift register. The slave waits for a read of the SR1 register followed by a write in the DR register, holding the SCL line low (see Figure 68: Transfer sequencing EV3). When the acknowledge pulse is received:
The EVF and BTF bits are set by hardware with an interrupt if the ITE bit is set.
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I2C bus interface (I2C)
ST72321Bxxx-Auto
Closing slave communication
After the last data byte is transferred, a Stop Condition is generated by the master. The interface detects this condition and sets:
EVF and STOPF bits with an interrupt if the ITE bit is set.
Then the interface waits for a read of the SR2 register (see Figure 68: Transfer sequencing EV4).
Error cases
BERR: Detection of a Stop or a Start condition during a byte transfer. In this case, the EVF and the BERR bits are set with an interrupt if the ITE bit is set. If it is a Stop then the interface discards the data, released the lines and waits for another Start condition. If it is a Start then the interface discards the data and waits for the next slave address on the bus. AF: Detection of a non-acknowledge bit. In this case, the EVF and AF bits are set with an interrupt if the ITE bit is set. The AF bit is cleared by reading the I2CSR2 register. However, if read before the completion of the transmission, the AF flag will be set again, thus possibly generating a new interrupt. Software must ensure either that the SCL line is back at 0 before reading the SR2 register, or be able to correctly handle a second interrupt during the 9th pulse of a transmitted byte.
Note:
In case of errors, the SCL line is not held low; however, the SDA line can remain low if the last bits transmitted are all 0. While AF = 1, the SCL line may be held low due to SB or BTF flags that are set at the same time. It is then necessary to release both lines by software. How to release the SDA / SCL lines Set and subsequently clear the STOP bit while BTF is set. The SDA/SCL lines are released after the transfer of the current byte. SMBus compatibility The ST7 I2C is compatible with the SMBus V1.1 protocol. It supports all SMBus addressing modes, SMBus bus protocols and CRC-8 packet error checking. Refer to SMBus Slave Driver For ST7 I2C Peripheral (AN1713).
16.4.2
Master mode
To switch from default Slave mode to Master mode a Start condition generation is needed.
Start condition
Setting the START bit while the BUSY bit is cleared causes the interface to switch to Master mode (M/SL bit set) and generates a Start condition. Once the Start condition is sent:
The EVF and SB bits are set by hardware with an interrupt if the ITE bit is set.
Then the master waits for a read of the SR1 register followed by a write in the DR register with the Slave address, holding the SCL line low (see Figure 68: Transfer sequencing EV5).
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ST72321Bxxx-Auto
I2C bus interface (I2C)
Slave address transmission
Then the slave address is sent to the SDA line via the internal shift register.

In 7-bit addressing mode, one address byte is sent. In 10-bit addressing mode, sending the first byte including the header sequence causes the following event: - The EVF bit is set by hardware with interrupt generation if the ITE bit is set.
Then the master waits for a read of the SR1 register followed by a write in the DR register, holding the SCL line low (see Figure 68: Transfer sequencing EV9). Then the second address byte is sent by the interface. After completion of this transfer (and acknowledge from the slave if the ACK bit is set):
The EVF bit is set by hardware with interrupt generation if the ITE bit is set.
Then the master waits for a read of the SR1 register followed by a write in the CR register (for example set PE bit), holding the SCL line low (see Figure 68: Transfer sequencing EV6). Next, the master must enter Receiver or Transmitter mode. Note: In 10-bit addressing mode, to switch the master to Receiver mode, software must generate a repeated Start condition and resend the header sequence with the least significant bit set (11110xx1).
Master receiver
Following the address transmission and after SR1 and CR registers have been accessed, the master receives bytes from the SDA line into the DR register via the internal shift register. After each byte the interface generates in sequence:

Acknowledge pulse if the ACK bit is set EVF and BTF bits are set by hardware with an interrupt if the ITE bit is set.
Then the interface waits for a read of the SR1 register followed by a read of the DR register, holding the SCL line low (see Figure 68: Transfer sequencing EV7). To close the communication: Before reading the last byte from the DR register, set the STOP bit to generate the Stop condition. The interface goes automatically back to slave mode (M/SL bit cleared). Note: In order to generate the non-acknowledge pulse after the last received data byte, the ACK bit must be cleared just before reading the second last data byte.
Master transmitter
Following the address transmission and after SR1 register has been read, the master sends bytes from the DR register to the SDA line via the internal shift register. The master waits for a read of the SR1 register followed by a write in the DR register, holding the SCL line low (see Figure 68: Transfer sequencing EV8). When the acknowledge bit is received, the interface sets:
EVF and BTF bits with an interrupt if the ITE bit is set.
To close the communication: After writing the last byte to the DR register, set the STOP bit to generate the Stop condition. The interface goes automatically back to slave mode (M/SL bit cleared).
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I2C bus interface (I2C)
ST72321Bxxx-Auto
Error cases
BERR: Detection of a Stop or a Start condition during a byte transfer. In this case, the EVF and BERR bits are set by hardware with an interrupt if ITE is set. Note that BERR will not be set if an error is detected during the first or second pulse of each 9-bit transaction: - Single Master Mode If a Start or Stop is issued during the first or second pulse of a 9-bit transaction, the BERR flag will not be set and transfer will continue however the BUSY flag will be reset. To work around this, slave devices should issue a NACK when they receive a misplaced Start or Stop. The reception of a NACK or BUSY by the master in the middle of communication makes it possible to re-initiate transmission. Multimaster Mode Normally the BERR bit would be set whenever unauthorized transmission takes place while transfer is already in progress. However, an issue will arise if an external master generates an unauthorized Start or Stop while the I2C master is on the first or second pulse of a 9-bit transaction. It is possible to work around this by polling the BUSY bit during I2C master mode transmission. The resetting of the BUSY bit can then be handled in a similar manner as the BERR flag being set.
-
AF: Detection of a non-acknowledge bit. In this case, the EVF and AF bits are set by hardware with an interrupt if the ITE bit is set. To resume, set the Start or Stop bit. The AF bit is cleared by reading the I2CSR2 register. However, if read before the completion of the transmission, the AF flag will be set again, thus possibly generating a new interrupt. Software must ensure either that the SCL line is back at 0 before reading the SR2 register, or be able to correctly handle a second interrupt during the 9th pulse of a transmitted byte. ARLO: Detection of an arbitration lost condition. In this case the ARLO bit is set by hardware (with an interrupt if the ITE bit is set and the interface goes automatically back to slave mode (the M/SL bit is cleared).
Note:
In all these cases, the SCL line is not held low; however, the SDA line can remain low due to possible `0' bits transmitted last. It is then necessary to release both lines by software.
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ST72321Bxxx-Auto Figure 68. Transfer sequencing
7-bit Slave receiver: S Address A EV1 7-bit Slave transmitter: S Address A EV1 EV3 7-bit Master receiver: S EV5 Address A EV6 Data1 A EV7 Data2 A EV7 ..... DataN Data1 A EV3 Data2 A EV3 ..... DataN Data1 A EV2 Data2 A EV2 ..... DataN A
I2C bus interface (I2C)
P EV2 EV4
NA EV3-1
P EV4
NA EV7
P
7-bit Master transmitter: S EV5 10-bit Slave receiver: S Header A Address A EV1 10-bit Slave transmitter: Sr Header A EV1 EV3 10-bit Master transmitter: S EV5 10-bit Master receiver: Sr EV5 Header A EV6 Data1 A EV7 ..... DataN A EV7 P Header A EV9 Address A EV6 EV8 Data1 A EV8 ..... DataN A EV8 P Data1 A .... DataN EV3 . A EV3-1 P EV4 Data1 A EV2 ..... DataN A EV2 P EV4 Address A EV6 EV8 Data1 A EV8 Data2 A EV8 ..... DataN A EV8 P
Legend: S = Start, Sr = Repeated Start, P = Stop, A = Acknowledge, NA = Non-acknowledge, EVx = Event (with interrupt if ITE = 1) EV1: EVF = 1, ADSL = 1, cleared by reading SR1 register. EV2: EVF = 1, BTF = 1, cleared by reading SR1 register followed by reading DR register. EV3: EVF = 1, BTF = 1, cleared by reading SR1 register followed by writing DR register. EV3-1: EVF = 1, AF = 1, BTF = 1; AF is cleared by reading SR1 register. BTF is cleared by releasing the lines (STOP = 1, STOP = 0) or by writing DR register (DR = FFh). Note: If lines are released by STOP = 1, STOP = 0, the subsequent EV4 is not seen. EV4: EVF = 1, STOPF = 1, cleared by reading SR2 register. EV5: EVF = 1, SB = 1, cleared by reading SR1 register followed by writing DR register. EV6: EVF = 1, cleared by reading SR1 register followed by writing CR register (for example PE = 1). EV7: EVF = 1, BTF = 1, cleared by reading SR1 register followed by reading DR register. EV8: EVF = 1, BTF = 1, cleared by reading SR1 register followed by writing DR register. EV9: EVF = 1, ADD10 = 1, cleared by reading SR1 register followed by writing DR register.
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I2C bus interface (I2C)
ST72321Bxxx-Auto
16.5
Low power modes
Table 80.
Mode
2
Effect of low power modes on I2C
Effect No effect on I C interface. I2C interrupts cause the device to exit from Wait mode. I2C registers are frozen. In Halt mode, the I2C interface is inactive and does not acknowledge data on the bus. The I2C interface resumes operation when the MCU is woken up by an interrupt with "exit from Halt mode" capability.
Wait
Halt
16.6
Interrupts
Figure 69. Interrupt control logic diagram
ADD10 BTF ADSL SB AF STOPF ARLO BERR * * EVF can also be set by EV6 or an error from the SR2 register. ITE
INTERRUPT
EVF
Table 81.
I2C interrupt control/wake-up capability
Interrupt event Event flag ADD10 BTF ADSEL SB ITE Yes No AF STOPF ARLO BERR Enable Exit from control bit Wait Exit from Halt
10-bit Address Sent Event (Master mode) End of Byte Transfer Event Address Matched Event (Slave mode) Start Bit Generation Event (Master mode) Acknowledge Failure Event Stop Detection Event (Slave mode) Arbitration Lost Event (Multimaster configuration) Bus Error Event
Note:
The I2C interrupt events are connected to the same interrupt vector (see Interrupts chapter). They generate an interrupt if the corresponding Enable Control bit is set and the I-bit in the CC register is reset (RIM instruction).
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ST72321Bxxx-Auto
I2C bus interface (I2C)
16.7
16.7.1
Register description
I2C control register (CR)
CR 7 Reserved 6 5 PE RW 4 ENGC RW 3 START RW 2 ACK RW Reset value: 0000 0000 (00h) 1 STOP RW 0 ITE RW
Table 82.
Bit 7:6 Name -
CR register description
Function Reserved. Forced to 0 by hardware. Peripheral enable This bit is set and cleared by software. 0: Peripheral disabled 1: Master/Slave capability Notes: - When PE = 0, all the bits of the CR register and the SR register except the Stop bit are reset. All outputs are released while PE = 0 - When PE = 1, the corresponding I/O pins are selected by hardware as alternate functions. To enable the I2C interface, write the CR register TWICE with PE = 1 as the first write only activates the interface (only PE is set).
5
PE
4
Enable General Call This bit is set and cleared by software. It is also cleared by hardware when the interface is disabled (PE = 0). The 00h General Call address is acknowledged (01h ignored). ENGC 0: General Call disabled 1: General Call enabled Note: In accordance with the I2C standard, when GCAL addressing is enabled, an I2C slave can only receive data. It will not transmit data to the master. Generation of a Start condition This bit is set and cleared by software. It is also cleared by hardware when the interface is disabled (PE = 0) or when the Start condition is sent (with interrupt generation if ITE = 1). In Master mode START 0: No start generation 1: Repeated start generation In Slave mode 0: No start generation 1: Start generation when the bus is free Acknowledge enable This bit is set and cleared by software. It is also cleared by hardware when the interface is disabled (PE = 0). 0: No acknowledge returned 1: Acknowledge returned after an address byte or a data byte is received
3
2
ACK
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I2C bus interface (I2C) Table 82.
Bit Name
ST72321Bxxx-Auto CR register description (continued)
Function Generation of a Stop condition This bit is set and cleared by software. It is also cleared by hardware in master mode. Note: This bit is not cleared when the interface is disabled (PE = 0). In Master mode 0: No stop generation 1: Stop generation after the current byte transfer or after the current Start condition is sent. The STOP bit is cleared by hardware when the Stop condition is sent. In Slave mode 0: No stop generation 1: Release the SCL and SDA lines after the current byte transfer (BTF = 1). In this mode the STOP bit has to be cleared by software. Interrupt enable This bit is set and cleared by software and cleared by hardware when the interface is disabled (PE = 0). 0: Interrupts disabled 1: Interrupts enabled Refer to Figure 69 and Table 81 for the relationship between the events and the interrupt. SCL is held low when the ADD10, SB, BTF or ADSL flags or an EV6 event (see Figure 68) is detected.
1
STOP
0
ITE
16.7.2
I2C status register 1 (SR1)
SR1 7 EVF RO 6 ADD10 RO 5 TRA RO 4 BUSY RO 3 BTF RO 2 ADSL RO Reset value: 0000 0000 (00h) 1 M/SL RO 0 SB RO
Table 83.
Bit Name
SR1 register description
Function Event flag This bit is set by hardware as soon as an event occurs. It is cleared by software reading SR2 register in case of error event or as described in Figure 68. It is also cleared by hardware when the interface is disabled (PE = 0). 0: No event 1: One of the following events has occurred: - BTF = 1 (Byte received or transmitted) - ADSL = 1 (Address matched in Slave mode while ACK = 1) - SB = 1 (Start condition generated in Master mode) - AF = 1 (No acknowledge received after byte transmission) - STOPF = 1 (Stop condition detected in Slave mode) - ARLO = 1 (Arbitration lost in Master mode) - BERR = 1 (Bus error, misplaced Start or Stop condition detected) - ADD10 = 1 (Master has sent header byte) - Address byte successfully transmitted in Master mode
7
EVF
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ST72321Bxxx-Auto Table 83.
Bit Name
I2C bus interface (I2C) SR1 register description (continued)
Function
6
10-bit addressing in Master mode This bit is set by hardware when the master has sent the first byte in 10-bit address mode. It is cleared by software reading SR2 register followed by a write in the DR ADD10 register of the second address byte. It is also cleared by hardware when the peripheral is disabled (PE = 0). 0: No ADD10 event occurred. 1: Master has sent first address byte (header) Transmitter/Receiver When BTF is set, TRA = 1 if a data byte has been transmitted. It is cleared automatically when BTF is cleared. It is also cleared by hardware after detection of Stop condition (STOPF = 1), loss of bus arbitration (ARLO = 1) or when the interface is disabled (PE = 0). 0: Data byte received (if BTF = 1) 1: Data byte transmitted
5
TRA
4
Bus busy This bit is set by hardware on detection of a Start condition and cleared by hardware on detection of a Stop condition. It indicates a communication in progress on the bus. The BUSY flag of the I2CSR1 register is cleared if a Bus Error occurs. 0: No communication on the bus BUSY 1: Communication ongoing on the bus Note: The BUSY flag is NOT updated when the interface is disabled (PE = 0). This can have consequences when operating in Multimaster mode; that is, a second active I2C master commencing a transfer with an unset BUSY bit can cause a conflict resulting in lost data. A software workaround consists of checking that the I2C is not busy before enabling the I2C Multimaster cell. Byte transfer finished This bit is set by hardware as soon as a byte is correctly received or transmitted with interrupt generation if ITE = 1. It is cleared by software reading SR1 register followed by a read or write of DR register. It is also cleared by hardware when the interface is disabled (PE = 0). Following a byte transmission, this bit is set after reception of the acknowledge clock pulse. In case an address byte is sent, this bit is set only after the EV6 event (see Figure 68). BTF is cleared by reading SR1 register followed by writing the next byte in DR register. Following a byte reception, this bit is set after transmission of the acknowledge clock pulse if ACK = 1. BTF is cleared by reading SR1 register followed by reading the byte from DR register. The SCL line is held low while BTF = 1. 0: Byte transfer not done 1: Byte transfer succeeded
3
BTF
2
Address matched (Slave mode) This bit is set by hardware as soon as the received slave address matched with the OAR register content or a general call is recognized. An interrupt is generated if ITE = 1. It is cleared by software reading SR1 register or by hardware when the ADSL interface is disabled (PE = 0). The SCL line is held low while ADSL = 1. 0: Address mismatched or not received 1: Received address matched
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I2C bus interface (I2C) Table 83.
Bit Name
ST72321Bxxx-Auto SR1 register description (continued)
Function Master/Slave This bit is set by hardware as soon as the interface is in Master mode (writing START = 1). It is cleared by hardware after detecting a Stop condition on the bus or a loss of arbitration (ARLO = 1). It is also cleared when the interface is disabled (PE = 0). 0: Slave mode 1: Master mode Start bit (Master mode) This bit is set by hardware as soon as the Start condition is generated (following a write START = 1). An interrupt is generated if ITE = 1. It is cleared by software reading SR1 register followed by writing the address byte in DR register. It is also cleared by hardware when the interface is disabled (PE = 0). 0: No Start condition 1: Start condition generated
1
M/SL
0
SB
16.7.3
I2C status register 2 (SR2)
SR2 7 6 Reserved 5 4 AF RO 3 STOPF RO 2 ARLO RO Reset value: 0000 0000 (00h) 1 BERR RO 0 GCAL RO
Table 84.
Bit 7:5 Name -
SR2 register description
Function Reserved. Forced to 0 by hardware. Acknowledge failure This bit is set by hardware when no acknowledge is returned. An interrupt is generated if ITE = 1. It is cleared by software reading SR2 register or by hardware when the interface is disabled (PE = 0). The SCL line is not held low while AF = 1 but by other flags (SB or BTF) that are set at the same time. 0: No acknowledge failure 1: Acknowledge failure Note: When an AF event occurs, the SCL line is not held low; however, the SDA line can remain low if the last bits transmitted are all 0. It is then necessary to release both lines by software.
4
AF
3
Stop detection (Slave mode) This bit is set by hardware when a Stop condition is detected on the bus after an acknowledge (if ACK = 1). An interrupt is generated if ITE = 1. It is cleared by software reading SR2 register or by hardware when the interface is disabled STOPF (PE = 0). The SCL line is not held low while STOPF = 1. 0: No Stop condition detected 1: Stop condition detected
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ST72321Bxxx-Auto Table 84.
Bit Name
I2C bus interface (I2C) SR2 register description (continued)
Function
2
Arbitration lost This bit is set by hardware when the interface loses the arbitration of the bus to another master. An interrupt is generated if ITE = 1. It is cleared by software reading SR2 register or by hardware when the interface is disabled (PE = 0). After an ARLO event the interface switches back automatically to Slave mode (M/SL = 0). The SCL line is not held low while ARLO = 1. ARLO 0: No arbitration lost detected 1: Arbitration lost detected Note: In a Multimaster environment, when the interface is configured in Master Receive mode it does not perform arbitration during the reception of the Acknowledge bit. Mishandling of the ARLO bit from the I2CSR2 register may occur when a second master simultaneously requests the same data from the same slave and the I2C master does not acknowledge the data. The ARLO bit is then left at 0 instead of being set. Bus error This bit is set by hardware when the interface detects a misplaced Start or Stop condition. An interrupt is generated if ITE = 1. It is cleared by software reading SR2 register or by hardware when the interface is disabled (PE = 0). The SCL line is not held low while BERR = 1. BERR 0: No misplaced Start or Stop condition 1: Misplaced Start or Stop condition Note: If a Bus Error occurs, a Stop or a repeated Start condition should be generated by the Master to re-synchronize communication, get the transmission acknowledged and the bus released for further communication. General Call (Slave mode) This bit is set by hardware when a general call address is detected on the bus while ENGC = 1. It is cleared by hardware detecting a Stop condition (STOPF = 1) or GCAL when the interface is disabled (PE = 0). 0: No general call address detected on bus 1: General call address detected on bus
1
0
16.7.4
I2C clock control register (CCR)
CCR 7 FM/SM RW 6 5 4 3 CC[6:0] RW 2 Reset value: 0000 0000 (00h) 1 0
Table 85.
Bit Name
CCR register description
Function
2C
7
Fast/Standard I mode This bit is set and cleared by software. It is not cleared when the interface is FM/SM disabled (PE = 0). 0: Standard I2C mode 1: Fast I2C mode
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I2C bus interface (I2C) Table 85.
Bit Name
ST72321Bxxx-Auto CCR register description (continued)
Function
7-bit clock divider These bits select the speed of the bus (fSCL) depending on the I2C mode. They are 6:0 CC[6:0] not cleared when the interface is disabled (PE = 0). Refer to the Electrical characteristics chapter for the table of values. Note: The programmed fSCL assumes no load on SCL and SDA lines.
16.7.5
I2C data register (DR)
DR 7 6 5 4 D[7:0] RW 3 2 Reset value: 0000 0000 (00h) 1 0
Table 86.
Bit Name
DR register description
Function 8-bit Data Register These bits contain the byte to be received or transmitted on the bus. Transmitter mode: Byte transmission start automatically when the software writes in the DR register. Receiver mode: The first data byte is received automatically in the DR register using the least significant bit of the address. Then, the following data bytes are received one by one after reading the DR register.
7:0
D[7:0]
16.7.6
I2C own address register (OAR1)
OAR1 7 ADD7 RW 6 ADD6 RW 5 ADD5 RW 4 ADD4 RW 3 ADD3 RW 2 ADD2 RW Reset value: 0000 0000 (00h) 1 ADD1 RW 0 ADD0 RW
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ST72321Bxxx-Auto Table 87.
Bit Name 7-bit addressing mode Interface address These bits define the I2C bus address 7:1 ADD[7:1] of the interface. They are not cleared when the interface is disabled (PE = 0). Address direction bit This bit is `don't care', the interface acknowledges either 0 or 1. It is not cleared when the interface is disabled (PE = 0). Address 01h is always ignored.
I2C bus interface (I2C) OAR1 register description
Function 10-bit addressing mode
Not applicable
0
ADD0
7:0 ADD[7:0]
Not applicable
Interface address These are the least significant bits of the I2C bus address of the interface. They are not cleared when the interface is disabled (PE = 0).
16.7.7
I2C own address register (OAR2)
OAR2 7 FR[1:0] RW 6 5 4 Reserved 3 2 ADD[9:8] RW Reset value: 0100 0000 (40h) 1 0 Reserved -
Table 88.
Bit
OAR2 register description
Function Frequency bits These bits are set by software only when the interface is disabled (PE = 0). To configure the interface to I2C specified delays, select the value corresponding to the CPU frequency fCPU. 00: fCPU < 6 MHz 01: fCPU = 6 to 8 MHz Reserved Interface address These are the most significant bits of the I2C bus address of the interface (10-bit mode only). They are not cleared when the interface is disabled (PE = 0). Reserved
Name
7:6
FR[1:0]
5:3 2:1 0
ADD[9:8] -
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I2C bus interface (I2C) Table 89.
Address (Hex.) 0018h 0019h 001Ah 001Bh 001Ch 001Dh 001Eh
ST72321Bxxx-Auto I2C register map and reset values
Register label 7 6 5 PE 0 TRA 0 0 CC5 0 ADD5 0 0 0 4 ENGC 0 BUSY 0 AF 0 CC4 0 ADD4 0 0 0 3 START 0 BTF 0 STOPF 0 CC3 0 ADD3 0 0 0 2 ACK 0 ADSL 0 ARLO 0 CC2 0 ADD2 0 ADD9 0 0 1 STOP 0 M/SL 0 BERR 0 CC1 0 ADD1 0 ADD8 0 0 0 ITE 0 SB 0 GCAL 0 CC0 0 ADD0 0 0 LSB 0
I2CCR Reset value I2CSR1 Reset value I2CSR2 Reset value I2CCCR Reset value I2COAR1 Reset value I2COAR2 Reset value I2CDR Reset value
0 EVF 0 0 FM/SM 0 ADD7 0 FR1 0 MSB 0
0 ADD10 0 0 CC6 0 ADD6 0 FR0 1 0
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ST72321Bxxx-Auto
10-bit A/D converter (ADC)
17
17.1
10-bit A/D converter (ADC)
Introduction
The on-chip Analog to Digital Converter (ADC) peripheral is a 10-bit, successive approximation converter with internal sample and hold circuitry. This peripheral has up to 16 multiplexed analog input channels (refer to device pin out description) that allow the peripheral to convert the analog voltage levels from up to 16 different sources. The result of the conversion is stored in a 10-bit data register. The A/D converter is controlled through a control/status register.
17.2
Main features

10-bit conversion Up to 16 channels with multiplexed input Linear successive approximation Data register (DR) which contains the results Conversion complete status flag On/off bit (to reduce consumption)
The block diagram is shown in Figure 70. Figure 70. ADC block diagram
fCPU DIV 4 DIV 2 0 1
fADC
EOC
SPEED ADON
0
CH3
CH2
CH1
CH0
ADCCSR
4
AIN0 AIN1 ANALOG MUX AINx
ANALOG TO DIGITAL CONVERTER
ADCDRH
D9
D8
D7
D6
D5
D4
D3
D2
ADCDRL
0
0
0
0
0
0
D1
D0
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10-bit A/D converter (ADC)
ST72321Bxxx-Auto
17.3
Functional description
The conversion is monotonic, meaning that the result never decreases if the analog input does not and never increases if the analog input does not. If the input voltage (VAIN) is greater than VAREF (high-level voltage reference) then the conversion result is FFh in the ADCDRH register and 03h in the ADCDRL register (without overflow indication). If the input voltage (VAIN) is lower than VSSA (low-level voltage reference) then the conversion result in the ADCDRH and ADCDRL registers is 00 00h. The A/D converter is linear and the digital result of the conversion is stored in the ADCDRH and ADCDRL registers. The accuracy of the conversion is described in Chapter 19: Electrical characteristics. RAIN is the maximum recommended impedance for an analog input signal. If the impedance is too high, this will result in a loss of accuracy due to leakage and sampling not being completed in the allotted time.
17.3.1
A/D converter configuration
The analog input ports must be configured as input, no pull-up, no interrupt. Refer to the Chapter 9: I/O ports. Using these pins as analog inputs does not affect the ability of the port to be read as a logic input. In the ADCCSR register:
Select the CS[3:0] bits to assign the analog channel to convert.
17.3.2
Starting the conversion
In the ADCCSR register:
Set the ADON bit to enable the A/D converter and to start the conversion. From this time on, the ADC performs a continuous conversion of the selected channel. The EOC bit is set by hardware. The result is in the ADCDR registers.
When a conversion is complete:

A read to the ADCDRH or a write to any bit of the ADCCSR register resets the EOC bit. To read the 10 bits, perform the following steps: 1. 2. 3. Note: Poll the EOC bit. Read the ADCDRL register. Read the ADCDRH register. This clears EOC automatically.
The data is not latched, so both the low and the high data register must be read before the next conversion is complete, so it is recommended to disable interrupts while reading the conversion result. To read only 8 bits, perform the following steps: 1. 2. Poll the EOC bit. Read the ADCDRH register. This clears EOC automatically.
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ST72321Bxxx-Auto
10-bit A/D converter (ADC)
17.3.3
Changing the conversion channel
The application can change channels during conversion. When software modifies the CH[3:0] bits in the ADCCSR register, the current conversion is stopped, the EOC bit is cleared, and the A/D converter starts converting the newly selected channel.
17.4
Note:
Low power modes
The A/D converter may be disabled by resetting the ADON bit. This feature allows reduced power consumption when no conversion is needed and between single shot conversions. Table 90.
Mode Wait Halt No effect on A/D converter A/D converter disabled. After wake-up from Halt mode, the A/D converter requires a stabilization time tSTAB (see Electrical characteristics) before accurate conversions can be performed.
Effect of low power modes on ADC
Effect
17.5
Interrupts
None.
17.6
17.6.1
ADC registers
Control/status register (ADCCSR)
ADCCSR 7 EOC RO 6 SPEED RW 5 ADON RW 4 Reserved 3 2 CH[3:0] RW Reset value: 0000 0000 (00h) 1 0
Table 91.
Bit Name
ADCCSR register description
Function End of Conversion This bit is set by hardware. It is cleared by hardware when software reads the ADCDRH register or writes to any bit of the ADCCSR register. 0: Conversion is not complete 1: Conversion complete
7
EOC
6
ADC clock selection This bit is set and cleared by software. SPEED 0: fADC = fCPU/4 1: fADC = fCPU/2
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10-bit A/D converter (ADC) Table 91.
Bit Name
ST72321Bxxx-Auto
ADCCSR register description (continued)
Function
5
A/D Converter on This bit is set and cleared by software. ADON 0: Disable ADC and stop conversion 1: Enable ADC and start conversion Reserved. Must be kept cleared
4
Channel Selection These bits are set and cleared by software. They select the analog input to convert. 0000: Channel pin = AIN0 0001: Channel pin = AIN1 0010: Channel pin = AIN2 0011: Channel pin = AIN3 0100: Channel pin = AIN4 0101: Channel pin = AIN5 0110: Channel pin = AIN6 0111: Channel pin = AIN7 3:0 CH[3:0] 1000: Channel pin = AIN8 1001: Channel pin = AIN9 1010: Channel pin = AIN10 1011: Channel pin = AIN11 1100: Channel pin = AIN12 1101: Channel pin = AIN13 1110: Channel pin = AIN14 1111: Channel pin = AIN15 Note: The number of channels is device dependent. Refer to the device pinout description.
17.6.2
Data register (ADCDRH)
ADCDRH 7 6 5 4 D[9:2] RO 3 2 Reset value: 0000 0000 (00h) 1 0
Table 92.
Bit 7:0 Name D[9:2]
ADCDRH register description
Function MSB of Converted Analog Value
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ST72321Bxxx-Auto
10-bit A/D converter (ADC)
17.6.3
Data register (ADCDRL)
ADCDRL 7 6 5 Reserved 4 3 2 Reset value: 0000 0000 (00h) 1 D[1:0] RO 0
Table 93.
Bit 7:2 1:0 Name D[1:0]
ADCDRL register description
Function Reserved. Forced by hardware to 0. LSB of Converted Analog Value
17.6.4
ADC register map and reset values
Table 94.
Address (Hex.) 0070h 0071h 0072h
ADC register map and reset values
Register label ADCCSR Reset value ADCDRH Reset value ADCDRL Reset value 7 EOC 0 D9 0 0 6 SPEED 0 D8 0 0 5 ADON 0 D7 0 0 4 3 CH3 0 D5 0 0 2 CH2 0 D4 0 0 1 CH1 0 D3 0 D1 0 0 CH0 0 D2 0 D0 0
0 D6 0 0
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Instruction set
ST72321Bxxx-Auto
18
18.1
Instruction set
CPU addressing modes
The CPU features 17 different addressing modes which can be classified in seven main groups as listed in the following table: Table 95. Addressing modes
Group Inherent Immediate Direct Indexed Indirect Relative Bit operation NOP LD A,#$55 LD A,$55 LD A,($55,X) LD A,([$55],X) JRNE loop BSET byte,#5 Example
The CPU instruction set is designed to minimize the number of bytes required per instruction: To do so, most of the addressing modes may be divided in two submodes called long and short:

Long addressing mode is more powerful because it can use the full 64 Kbyte address space; however, it uses more bytes and more CPU cycles. Short addressing mode is less powerful because it can generally only access page zero (0000h - 00FFh range), but the instruction size is more compact, and faster. All memory to memory instructions use short addressing modes only (CLR, CPL, NEG, BSET, BRES, BTJT, BTJF, INC, DEC, RLC, RRC, SLL, SRL, SRA, SWAP).
The ST7 Assembler optimizes the use of long and short addressing modes. Table 96. CPU addressing mode overview
Mode Inherent Immediate Short Long No Offset Short Long Short Long Short Direct Direct Direct Direct Direct Indirect Indirect Indirect Indexed Indexed Indexed Indexed nop ld A,#$55 ld A,$10 ld A,$1000 ld A,(X) ld A,($10,X) ld A,($1000,X) ld A,[$10] ld A,[$10.w] ld A,([$10],X) 00..FF 0000..FFFF 00..FF 00..1FE 0000..FFFF 00..FF 0000..FFFF 00..1FE 00..FF 00..FF 00..FF byte word byte Syntax Destination Pointer address (Hex.) Pointer size (Hex.) Length (bytes) +0 +1 +1 +2 +0 +1 +2 +2 +2 +2
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ST72321Bxxx-Auto Table 96. CPU addressing mode overview (continued)
Mode Long Relative Relative Bit Bit Bit Bit Indirect Direct Indirect Direct Indirect Direct Indirect Relative Relative Indexed Syntax ld A,([$10.w],X) jrne loop jrne [$10] bset $10,#7 bset [$10],#7 btjt $10,#7,skip Destination 0000..FFFF PC+/-127 PC+/-127 00..FF 00..FF 00..FF 00..FF 00..FF 00..FF Pointer address (Hex.) 00..FF
Instruction set
Pointer size (Hex.) word
Length (bytes) +2 +1
byte
+2 +1
byte
+2 +2
btjt [$10],#7,skip 00..FF
byte
+3
18.1.1
Inherent
All Inherent instructions consist of a single byte. The opcode fully specifies all the required information for the CPU to process the operation. Table 97. Inherent instructions
Instruction NOP TRAP WFI HALT RET IRET SIM RIM SCF RCF RSP LD CLR PUSH/POP INC/DEC TNZ CPL, NEG MUL SLL, SRL, SRA, RLC, RRC SWAP No operation S/W Interrupt Wait For Interrupt (Low Power Mode) Halt Oscillator (Lowest Power Mode) Sub-routine Return Interrupt Sub-routine Return Set Interrupt Mask (level 3) Reset Interrupt Mask (level 0) Set Carry Flag Reset Carry Flag Reset Stack Pointer Load Clear Push/Pop to/from the stack Increment/Decrement Test Negative or Zero 1 or 2 Complement Byte Multiplication Shift and Rotate Operations Swap Nibbles Function
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Instruction set
ST72321Bxxx-Auto
18.1.2
Immediate
Immediate instructions have 2 bytes. The first byte contains the opcode and the second byte contains the operand value. Table 98. Immediate instructions
Instruction LD CP BCP AND, OR, XOR ADC, ADD, SUB, SBC Load Compare Bit Compare Logical Operations Arithmetic Operations Function
18.1.3
Direct
In Direct instructions, the operands are referenced by their memory address. The direct addressing mode consists of two submodes:
Direct (short)
The address is a byte, thus requires only one byte after the opcode, but only allows 00 - FF addressing space.
Direct (long)
The address is a word, thus allowing 64 Kbyte addressing space, but requires 2 bytes after the opcode.
18.1.4
Indexed (no offset, short, long)
In this mode, the operand is referenced by its memory address, which is defined by the unsigned addition of an index register (X or Y) with an offset. The indexed addressing mode consists of three submodes:
Indexed (no offset)
There is no offset, (no extra byte after the opcode), and allows 00 - FF addressing space.
Indexed (short)
The offset is a byte, thus requires only one byte after the opcode and allows 00 - 1FE addressing space.
Indexed (long)
The offset is a word, thus allowing 64 Kbyte addressing space and requires 2 bytes after the opcode.
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ST72321Bxxx-Auto
Instruction set
18.1.5
Indirect (short, long)
The required data byte to do the operation is found by its memory address, located in memory (pointer). The pointer address follows the opcode. The indirect addressing mode consists of two submodes:
Indirect (short)
The pointer address is a byte, the pointer size is a byte, thus allowing 00 - FF addressing space, and requires 1 byte after the opcode.
Indirect (long)
The pointer address is a byte, the pointer size is a word, thus allowing 64 Kbyte addressing space, and requires 1 byte after the opcode.
18.1.6
Indirect indexed (short, long)
This is a combination of indirect and short indexed addressing modes. The operand is referenced by its memory address, which is defined by the unsigned addition of an index register value (X or Y) with a pointer value located in memory. The pointer address follows the opcode. The indirect indexed addressing mode consists of two submodes:
Indirect indexed (short)
The pointer address is a byte, the pointer size is a byte, thus allowing 00 - 1FE addressing space, and requires 1 byte after the opcode.
Indirect indexed (long)
The pointer address is a byte, the pointer size is a word, thus allowing 64 Kbyte addressing space, and requires 1 byte after the opcode. Table 99. Instructions supporting direct, indexed, indirect, and indirect indexed addressing modes
Type LD CP Long and short instructions AND, OR, XOR ADC, ADD, SUB, SBC BCP Instruction Load Compare Logical operations Arithmetic Additions/Subtractions operations Bit Compare Function
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Instruction set Table 99.
ST72321Bxxx-Auto Instructions supporting direct, indexed, indirect, and indirect indexed addressing modes (continued)
Type CLR INC, DEC TNZ CPL, NEG Instruction Clear Increment/Decrement Test Negative or Zero 1 or 2 Complement Bit Operations Bit Test and Jump Operations Function
Short instructions only
BSET, BRES BTJT, BTJF
SLL, SRL, SRA, RLC, RRC Shift and Rotate Operations SWAP CALL, JP Swap Nibbles Call or Jump subroutine
18.1.7
Relative (direct, indirect)
This addressing mode is used to modify the PC register value, by adding an 8-bit signed offset to it. Table 100. Available relative direct/indirect instructions
Instruction JRxx CALLR Conditional Jump Call Relative Function
The relative addressing mode consists of two submodes:
Relative (direct)
The offset is following the opcode.
Relative (indirect)
The offset is defined in memory, which address follows the opcode.
18.2
Instruction groups
The ST7 family devices use an Instruction Set consisting of 63 instructions. The instructions may be subdivided into 13 main groups as illustrated in the following table: Table 101. Instruction groups
Group Load and Transfer Stack operation Increment/Decrement Compare and Tests LD PUSH INC CP CLR POP DEC TNZ BCP RSP Instructions
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ST72321Bxxx-Auto Table 101. Instruction groups (continued)
Group Logical operations Bit Operation Conditional Bit Test and Branch Arithmetic operations Shift and Rotates Unconditional Jump or Call Conditional Branch Interruption management Condition Code Flag modification AND BSET BTJT ADC SLL JRA JRxx TRAP SIM WFI RIM HALT SCF IRET RCF OR BRES BTJF ADD SRL JRT SUB SRA JRF SBC RLC JP MUL RRC CALL XOR Instructions CPL NEG
Instruction set
SWAP CALLR
SLA NOP RET
18.2.1
Using a prebyte
The instructions are described with one to four opcodes. In order to extend the number of available opcodes for an 8-bit CPU (256 opcodes), three different prebyte opcodes are defined. These prebytes modify the meaning of the instruction they precede. The whole instruction becomes: PC - 2 PC - 1 PC PC + 1 End of previous instruction Prebyte Opcode Additional word (0 to 2) according to the number of bytes required to compute the effective address
These prebytes enable instruction in Y as well as indirect addressing modes to be implemented. They precede the opcode of the instruction in X or the instruction using direct addressing mode. The prebytes are: PDY 90 PIX 92 Replace an X based instruction using immediate, direct, indexed, or inherent addressing mode by a Y one. Replace an instruction using direct, direct bit, or direct relative addressing mode to an instruction using the corresponding indirect addressing mode. It also changes an instruction using X indexed addressing mode to an instruction using indirect X indexed addressing mode. Replace an instruction using X indirect indexed addressing mode by a Y one.
PIY 91
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Instruction set Table 102. Instruction set overview
Mnemo ADC ADD AND BCP BRES BSET BTJF BTJT CALL Description Add with Carry Addition Logical And Bit compare A, Memory Bit Reset Bit Set Jump if bit is false (0) Jump if bit is true (1) Call subroutine Function/Example A=A+M+C A=A+M A=A.M tst (A . M) bres Byte, #3 bset Byte, #3 btjf Byte, #3, Jmp1 btjt Byte, #3, Jmp1 A A A A M M M M Dst M M M M Src I1
ST72321Bxxx-Auto
H H H
I0
N N N N N
Z Z Z Z Z
C C C
C C
CALLR Call subroutine relative CLR CP CPL DEC HALT IRET INC JP JRA JRT JRF JRIH JRIL JRH JRNH JRM JRNM JRMI JRPL JREQ JRNE JRC JRNC JRULT Clear Arithmetic Compare One Complement Decrement Halt Interrupt routine return Increment Absolute Jump Jump relative always Jump relative Never jump Jump if ext. INT pin = 1 Jump if ext. INT pin = 0 Jump if H = 1 Jump if H = 0 Jump if I1:0 = 11 Jump if I1:0 <> 11 Jump if N = 1 (minus) Jump if N = 0 (plus) Jump if Z = 1 (equal) Jump if Z = 0 (not equal) Jump if C = 1 Jump if C = 0 Jump if C = 1 jrf * (ext. INT pin high) (ext. INT pin low) H=1? H=0? I1:0 = 11 ? I1:0 <> 11 ? N=1? N=0? Z=1? Z=0? C=1? C=0? Unsigned < Jmp if unsigned >= Pop CC, A, X, PC inc X jp [TBL.w] reg, M tst(Reg - M) A = FFH-A dec Y reg, M reg reg, M reg, M 1 I1 H 0 I0 N N Z Z C M 0 N N N 1 Z Z Z C 1
JRUGE Jump if C = 0
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ST72321Bxxx-Auto Table 102. Instruction set overview (continued)
Mnemo Description Function/Example Unsigned > Unsigned <= dst <= src X,A = X * A neg $10 reg, M A, X, Y reg, M M, reg X, Y, A 0 Dst Src I1 H
Instruction set
I0
N
Z
C
JRUGT Jump if (C + Z = 0) JRULE LD MUL NEG NOP OR POP PUSH RCF RET RIM RLC RRC RSP SBC SCF SIM SLA SLL SRL SRA SUB SWAP TNZ TRAP WFI XOR Jump if (C + Z = 1) Load Multiply Negate (2's compl) No Operation OR operation Pop from the Stack
N
Z 0
N
Z
C
A=A+M pop reg pop CC
A reg CC M
M M M reg, CC I1 H I0
N
Z
N
Z
C
Push onto the Stack Reset carry flag Subroutine Return Enable Interrupts Rotate left true C Rotate right true C Reset Stack Pointer Subtract with Carry Set carry flag Disable Interrupts Shift left Arithmetic Shift left Logic Shift right Logic Shift right Arithmetic Subtraction SWAP nibbles Test for Neg & Zero S/W trap Wait for Interrupt Exclusive OR
push Y C=0
0
I1:0 = 10 (level 0) C <= A <= C C => A => C S = Max allowed A=A-M-C C=1 I1:0 = 11 (level 3) C <= A <= 0 C <= A <= 0 0 => A => C A7 => A => C A=A-M A7-A4 <=> A3-A0 tnz lbl1 S/W interrupt reg, M reg, M reg, M reg, M A reg, M M A M reg, M reg, M
1
0 N N Z Z C C
N
Z
C 1
1
1 N N 0 N N N N Z Z Z Z Z Z Z C C C C C
1 1
1 0 N Z
A = A XOR M
A
M
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Electrical characteristics
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19
19.1
Electrical characteristics
Parameter conditions
Unless otherwise specified, all voltages are referred to VSS.
19.1.1
Minimum and maximum values
Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at TA = 25C and TA = TAmax (given by the selected temperature range). Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean 3).
19.1.2
Typical values
Unless otherwise specified, typical data is based on TA = 25C, VDD = 5V. The typical values are given only as design guidelines and are not tested.
19.1.3
Typical curves
Unless otherwise specified, all typical curves are given only as design guidelines and are not tested.
19.1.4
Loading capacitor
The loading conditions used for pin parameter measurement are shown in Figure 71. Figure 71. Pin loading conditions
ST7 PIN
CL
19.1.5
Pin input voltage
The input voltage measurement on a pin of the device is described in Figure 72. Figure 72. Pin input voltage
ST7 PIN VIN
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19.2
Absolute maximum ratings
Stresses above those listed as "absolute maximum ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device under these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
19.2.1
Voltage characteristics
Table 103. Voltage characteristics
Symbol VDD - VSS VPP - VSS VIN(1) Supply voltage Programming voltage Input voltage on true open-drain pin Input voltage on any other pin Ratings Maximum value 6.5 13 V VSS - 0.3 to 6.5 VSS - 0.3 to VDD + 0.3 50 mV 50 See Section 19.7.3 on page 206. Electrostatic discharge voltage (Machine Model) Unit
|VDDx| and |VSSx| Variations between different digital power pins |VSSA - VSSx| VESD(HBM) VESD(MM) Variations between digital and analog ground pins Electrostatic discharge voltage (Human Body Model)
1. Directly connecting the RESET and I/O pins to VDD or VSS could damage the device if an unintentional internal reset is generated or an unexpected change of the I/O configuration occurs (for example, due to a corrupted program counter). To guarantee safe operation, this connection has to be done through a pull-up or pull-down resistor (typical: 4.7k for RESET, 10k for I/Os). For the same reason, unused I/O pins must not be directly tied to VDD or VSS.
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19.2.2
Current characteristics
Table 104. Current characteristics
Symbol IVDD IVSS Ratings Total current into VDD power lines (source)(1) Total current out of VSS ground lines (sink)(1) Output current sunk by any standard I/O and control pin IIO Output current sunk by any high sink I/O pin Output current source by any I/Os and control pin Injected current on VPP pin Injected current on RESET pin IINJ(PIN)(2)(3) Injected current on OSC1 and OSC2 pins Injected current on PC6 pin (Flash devices only) Injected current on any other pin IINJ(PIN)
(2) (4)(5)
Maximum value Unit 150 20 40 - 25 5 5 5 +5 5 pins)(4) 25 mA mA
Total injected current (sum of all I/O and control
1. All power (VDD) and ground (VSS) lines must always be connected to the external supply. 2. IINJ(PIN) must never be exceeded. This is implicitly ensured if VIN maximum is respected. If VIN maximum cannot be respected, the injection current must be limited externally to the IINJ(PIN) value. A positive injection is induced by VIN > VDD while a negative injection is induced by VIN < VSS. For true open-drain pads, there is no positive injection current, and the corresponding VIN maximum must always be respected. 3. Negative injection may disturb the analog performance of the device. See Note 1 in Table 135: ADC accuracy on page 223. 4. When several inputs are submitted to a current injection, the maximum IINJ(PIN) is the absolute sum of the positive and negative injected currents (instantaneous values). These results are based on characterization with IINJ(PIN) maximum current injection on four I/O port pins of the device. 5. True open-drain I/O port pins do not accept positive injection.
19.2.3
Thermal characteristics
Table 105. Thermal characteristics
Symbol TSTG TJ Ratings Storage temperature range Value -65 to +150 Unit C
Maximum junction temperature (see Section 20.2: Thermal characteristics on page 227)
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19.3
19.3.1
Operating conditions
General operating conditions
Table 106. General operating conditions
Symbol fCPU VDD Parameter Internal clock frequency Standard voltage range (except Flash Write/Erase) Operating voltage for Flash Write/Erase VPP = 11.4 to 12.6V A suffix version TA Ambient temperature range B suffix version(1) -40 Conditions Min 0 3.8 4.5 Max 8 5.5 V 5.5 85 105 125 C Unit MHz
C suffix version
1. Available only on ROM and FASTROM devices. Refer to Section 21.2: ROM device ordering information and transfer of customer code on page 232.
Figure 73. fCPU max versus VDD
fCPU [MHz]
8 FUNCTIONALITY NOT GUARANTEED IN THIS AREA 6 4 2 1 0 3.5 3.8 4.0 4.5 5.5
FUNCTIONALITY GUARANTEED IN THIS AREA (UNLESS OTHERWISE SPECIFIED IN THE TABLES OF PARAMETRIC DATA)
SUPPLY VOLTAGE [V]
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19.3.2
Operating conditions with low voltage detector (LVD)
Subject to general operating conditions for VDD, fCPU, and TA.
Table 107. Operating conditions with low voltage detector (LVD)
Symbol Parameter Conditions VD level = High in option byte Reset release threshold VIT+(LVD) (VDD rise) VD level = Med. in option byte
(2)
Min 4.0(1) 3.55
(1)
Typ 4.2 3.75 3.15 4.0 3.55 3.0 200
Max 4.5 4.0(1) 3.35(1) 4.25(1) 3.75(1) 3.15(1)
Unit
VD level = Low in option byte(2) VD level = High in option byte
2.95(1) 3.8 3.35(1) 2.8(1)
V
VIT-(LVD)
Reset generation threshold (VDD fall) LVD voltage threshold hysteresis VDD rise time(2)(3) VDD glitches filtered (not detected) by LVD(4)
VD level = Med. in option byte(2) VD level = Low in option byte(2) VIT+(LVD)-VIT-(LVD) LVD enabled
Vhys(LVD) VtPOR tg(VDD)
mV 100ms/V 40 ns
6s/V
1. Data based on characterization results, tested in production for ROM devices only 2. Data based on characterization results, not tested in production 3. When VtPOR is faster than 100s/V, the Reset signal is released after a delay of maximum 42s after VDD crosses the VIT+(LVD) threshold. 4. If the medium or low thresholds are selected, the detection may occur outside the specified operating voltage range. Below 3.8V, device operation is not guaranteed.
19.3.3
Auxiliary voltage detector (AVD) thresholds
Subject to general operating conditions for VDD, fCPU, and TA.
Table 108. Auxiliary voltage detector (AVD) thresholds
Symbol Parameter 10 AVDF flag toggle threshold (VDD rise) Conditions VD level = High in option byte VIT+(AVD) VD level = Med. in option byte VD level = Low in option byte VD level = High in option byte VIT-(AVD) 01 AVDF flag toggle threshold (VDD fall) VD level = Med. in option byte VD level = Low in option byte Vhys(AVD) AVD voltage threshold hysteresis VITVIT+(AVD)-VIT-(AVD) Min 4.4(1) 3.95(1) 3.4(1) 4.2(1) 3.75(1) 3.2(1) Typ 4.6 4.15 3.6 4.4 4.0 3.4 200 mV 450 Max 4.9(1) 4.4(1) 3.8(1) 4.65(1) 4.2(1) 3.6(1) V Unit
Voltage drop between AVD flag set VIT-(AVD)-VIT-(LVD) and LVD reset activated
1. Data based on characterization results, tested in production for ROM devices only
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19.3.4
External voltage detector (EVD) thresholds
Subject to general operating conditions for VDD, fCPU, and TA.
Table 109. External voltage detector (EVD) thresholds
Symbol VIT+(EVD) VIT-(EVD) Vhys(EVD) Parameter 10 AVDF flag toggle threshold (VDD rise(1) 01 AVDF flag toggle threshold (VDD fall) EVD voltage threshold hysteresis
(1)
Conditions
Min 1.15 1.1
Typ 1.26 1.2 200
Max 1.35
Unit V
1.3 mV
VIT+(EVD)-VIT-(EVD)
1. Data based on characterization results, not tested in production
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19.4
Supply current characteristics
The following current consumption specified for the ST7 functional operating modes over temperature range does not take into account the clock source current consumption. To obtain the total device consumption, the two current values must be added (except for Halt mode, for which the clock is stopped).
19.4.1
Current consumption
Table 110. Current consumption
Flash devices Symbol Parameter Conditions Typ Supply current in Run mode(2) fOSC = 2 MHz, fCPU = 1 MHz fOSC = 4 MHz, fCPU = 2 MHz fOSC = 8 MHz, fCPU = 4 MHz fOSC = 16 MHz, fCPU = 8 MHz fOSC = 2 MHz, fCPU = 62.5 kHz fOSC = 4 MHz, fCPU = 125 kHz fOSC = 8 MHz, fCPU = 250 kHz fOSC = 16 MHz, fCPU = 500 kHz fOSC = 2 MHz, fCPU = 1 MHz fOSC = 4 MHz, fCPU = 2 MHz fOSC = 8 MHz, fCPU = 4 MHz fOSC = 16 MHz, fCPU = 8 MHz fOSC = 2 MHz, fCPU = 62.5 kHz fOSC = 4 MHz, fCPU = 125 kHz fOSC = 8 MHz, fCPU = 250 kHz fOSC = 16 MHz, fCPU = 500 kHz -40C < TA < +85C -40C < TA < +125C fOSC = 2 MHz fOSC = 4 MHz fOSC = 8 MHz fOSC = 16 MHz 1.3 2.0 3.6 7.1 600 700 800 1100 0.8 1.2 2.0 3.5 580 650 770 1050 <1 5 415 430 460 550 Max(1) 3.0 5.0 8.0 15.0 2700 3000 3600 4000 3.0 4.0 5.0 7.0 1200 1300 1800 2000 10 50 525 550 600 700 ROM devices Typ 0.5 1.2 2.2 4.8 100 200 300 500 0.5 0.8 1.5 3.0 50 90 180 350 <1 <1 15 30 60 120 Max(1) 1.0 2.0 4.0 8.0 600 700 800 950 1.0 1.3 2.2 4.0 100 150 300 600 10 A 50 25 50 100 200 Unit
mA
Supply current in Slow mode(2)
A
Supply current in Wait mode(2) IDD Supply current in Slow Wait mode(2)
mA
A
Supply current in Halt mode(3)
Supply current in Active Halt mode(4)
A
1. Data based on characterization results, tested in production at VDD max. and fCPU max. 2. Measurements are done in the following conditions: - Program executed from RAM, CPU running with RAM access - All I/O pins in input mode with a static value at VDD or VSS (no load) - All peripherals in reset state - LVD disabled - Clock input (OSC1) driven by external square wave - In Slow and Slow Wait mode, fCPU is based on fOSC divided by 32 - To obtain the total current consumption of the device, add the clock source (Section 19.4.2) and the peripheral power consumption (Section 19.4.3). 3. All I/O pins in push-pull 0 mode (when applicable) with a static value at VDD or VSS (no load), LVD disabled. Data based on characterization results, tested in production at VDD max. and fCPU max. 4. Data based on characterization results, not tested in production. All I/O pins in push-pull 0 mode (when applicable) with a static value at VDD or VSS (no load); clock input (OSC1) driven by external square wave, LVD disabled. To obtain the total current consumption of the device, add the clock source consumption (Section 19.4.2).
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19.4.2
Supply and clock managers
The previous current consumption specified for the ST7 functional operating modes over temperature range does not take into account the clock source current consumption. To obtain the total device consumption, the two current values must be added (except for Halt mode). Table 111. Oscillators, PLL and LVD current consumption
Symbol Parameter Conditions Typ 625 see section 19.5.3 on page 200 360 VDD = 5V 150 300 Max Unit
IDD(RCINT) Supply current of internal RC oscillator IDD(RES) IDD(PLL) IDD(LVD) Supply current of resonator oscillator(1)(2) PLL supply current LVD supply current
A
1. Data based on characterization results done with the external components specified in Section 19.5.3, not tested in production 2. As the oscillator is based on a current source, the consumption does not depend on the voltage.
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19.4.3
On-chip peripherals
Measured on LQFP64 generic board TA = 25C, fCPU = 4 MHz. Table 112. On-chip peripherals current consumption
Symbol IDD(TIM) IDD(ART) IDD(SPI) IDD(SCI) IDD(I2C) IDD(ADC) Parameter 16-bit timer supply current(1) ART PWM supply current SPI supply current
(3) (2)
Conditions VDD = 5.0V VDD = 5.0V VDD = 5.0V VDD = 5.0V
Typ 50 75 400 175 400
Unit A A A A A
SCI supply current(4) I2C supply current(5) ADC supply current when converting(6)
VDD = 5.0V
1. Data based on a differential IDD measurement between reset configuration (timer counter running at fCPU/4) and timer counter stopped (only TIMD bit set). Data valid for one timer. 2. Data based on a differential IDD measurement between reset configuration (timer stopped) and timer counter enabled (only TCE bit set). 3. Data based on a differential IDD measurement between reset configuration (SPI disabled) and a permanent SPI master communication at maximum speed (data sent equal to 55h). This measurement includes the pad toggling consumption. 4. Data based on a differential IDD measurement between SCI low power state (SCID = 1) and a permanent SCI data transmit sequence. 5. Data based on a differential IDD measurement between reset configuration (I2C disabled) and a permanent I2C master communication at 100 kHz (data sent equal to 55h). This measurement includes the pad toggling consumption (27k ohm external pull-up on clock and data lines). 6. Data based on a differential IDD measurement between reset configuration and continuous A/D conversions.
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19.5
Clock and timing characteristics
Subject to general operating conditions for VDD, fCPU, and TA.
19.5.1
General timings
Table 113. General timings
Symbol tc(INST) Parameter Instruction cycle time fCPU = 8 MHz Interrupt reaction time(2) tv(IT) = tc(INST) + 10 250 10 fCPU = 8 MHz 1.25 375 1500 22 2.75 Conditions Min 2 Typ(1) 3 Max 12 Unit tCPU ns tCPU s
tv(IT)
1. Data based on typical application software. 2. Time measured between interrupt event and interrupt vector fetch. tc(INST) is the number of tCPU cycles needed to finish the current instruction execution.
19.5.2
External clock source
Table 114. External clock source
Symbol VOSC1H VOSC1L Parameter OSC1 input pin high level voltage OSC1 input pin low level voltage See Figure 74 Conditions Min 0.7xVDD VSS 5 ns 15 VSS < VIN < VDD 1 A Typ Max VDD 0.3xVDD Unit V
tw(OSC1H) OSC1 high or low time(1) tw(OSC1L) tr(OSC1) tf(OSC1) Ilkg OSC1 rise or fall time(1) OSC1 input leakage current
1. Data based on design simulation and/or technology characteristics, not tested in production.
Figure 74. Typical application with an external clock source
90% VOSC1H 10%
VOSC1L tr(OSC1) tf(OSC1) tw(OSC1H) tw(OSC1L)
OSC2
Not connected internally fOSC
EXTERNAL CLOCK SOURCE
OSC1
Ilkg ST72XXX
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19.5.3
Crystal and ceramic resonator oscillators
The ST7 internal clock can be supplied with four different crystal/ceramic resonator oscillators. All the information given in this paragraph is based on characterization results with specified typical external components. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and start-up stabilization time. Refer to the crystal/ceramic resonator manufacturer for more details (such as frequency, package or accuracy). Table 115. Crystal and ceramic resonator oscillators
Symbol Parameter LP: MP: MS: HS: Conditions Low power oscillator Medium power oscillator Medium speed oscillator High speed oscillator RS = 200 RS = 200 RS = 200 RS = 100 LP oscillator MP oscillator MS oscillator HS oscillator Min Typ Max Unit 1 >2 >4 >8 20 22 22 18 15 2 4 8 16 40 56 46 33 33 150 250 460 910
fOSC
Oscillator
frequency(1)
-
MHz
RF
Feedback resistor(2) Recommended load capacitance versus equivalent serial resistance of the crystal or ceramic resonator (RS)(3)
-
k
CL1 CL2
-
pF
i2
OSC2 driving current
LP oscillator MP oscillator VDD = 5V, VIN = VSS MS oscillator HS oscillator
-
80 160 310 610
A
1. The oscillator selection can be optimized in terms of supply current using a high-quality resonator with small RS value. Refer to crystal/ceramic resonator manufacturer for more details. 2. Data based on characterization results, not tested in production. The relatively low value of the RF resistor offers a good protection against issues resulting from use in a humid environment, due to the induced leakage and the bias condition change. However, it is recommended to take this point into account if the microcontroller is used in tough humidity conditions. 3. For CL1 and CL2 it is recommended to use high-quality ceramic capacitors in the 5pF to 25pF range (typ.) designed for high-frequency applications and selected to match the requirements of the crystal or resonator. CL1 and CL2, are usually the same size. The crystal manufacturer typically specifies a load capacitance which is the series combination of CL1 and CL2. PCB and MCU pin capacitance must be included when sizing CL1 and CL2 (10pF can be used as a rough estimate of the combined pin and board capacitance).
Figure 75. Typical application with a crystal or ceramic resonator
WHEN RESONATOR WITH INTEGRATED CAPACITORS CL1 OSC1
fOSC POWER DOWN LOGIC LINEAR AMPLIFIER FEEDBACK LOOP
RESONATOR RF CL2 OSC2
VDD/2 Ref
i2
ST72XXX
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Figure 76. Application with a crystal or ceramic resonator for ROM (LQFP64 or any 48/60K ROM)
WHEN RESONATOR WITH INTEGRATED CAPACITORS i2
fOSC CL1 OSC1
RESONATOR CL2 OSC2
RF
ST72XXX
Table 116. OSCRANGE selection for typical resonators
Typical ceramic resonators(1) Supplier fOSC (MHz) Reference 2 Murata 4 8 16 CSTCC2M00G56A-R0 CSTCR4M00G55B-R0 CSTCE8M00G55A-R0 HS mode CSTCE16M0G53A-R0
1. Resonator characteristics given by the ceramic resonator manufacturer. For more information on these resonators, please consult www.murata.com. 2. LP mode is not recommended for 2 MHz resonator because the peak to peak amplitude is too small (> 0.8V).
Recommended OSCRANGE option bit configuration MP mode(2) MS mode
19.5.4
RC oscillators
Table 117. RC oscillator characteristics
Symbol fOSC(RCINT) Parameter Internal RC oscillator frequency (see Figure 77) Conditions TA = 25C, VDD = 5V Min 2 Typ 3.5 Max 5.6 Unit MHz
Figure 77. Typical fOSC(RCINT) versus TA
4 fOSC(RCINT) (MHz) 3.8 3.6 3.4 3.2 3 -45 0 25 TA(C) 70 130 Vdd = 5V Vdd = 5.5V
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To reduce disturbance to the RC oscillator, it is recommended to place decoupling capacitors between VDD and VSS as shown in Figure 97.
19.5.5
PLL characteristics
Table 118. PLL characteristics
Symbol fOSC fCPU/fCPU Parameter PLL input frequency range Instantaneous PLL jitter(1) fOSC = 4 MHz Conditions Min 2 0.7 Typ Max 4 2 Unit MHz %
1. Data characterized but not tested
The user must take the PLL jitter into account in the application (for example, in serial communication or sampling of high frequency signals). The PLL jitter is a periodic effect, which is integrated over several CPU cycles. Therefore, the longer the period of the application signal, the less it is impacted by the PLL jitter. Figure 78 shows the PLL jitter integrated on application signals in the range 125 kHz to 4 MHz. At frequencies of less than 125 kHz, the jitter is negligible. Figure 78. Integrated PLL jitter versus signal frequency(1)
+/-Jitter (%) 1.2 FLASH typ 1 0.8 0.6 0.4 0.2 0 4 MHz 2 MHz 1 MHz 500 kHz 250 kHz 125 kHz Application Frequency ROM max ROM typ
1. Measurement conditions: fCPU = 8 MHz
19.6
19.6.1
Memory characteristics
RAM and hardware registers
Table 119. RAM supply voltage
Symbol VRM Parameter Data retention mode(1) Conditions Halt mode (or RESET) Min 1.6 Typ Max Unit V
1. Minimum VDD supply voltage without losing data stored in RAM (in Halt mode or under RESET) or in hardware registers (only in Halt mode). Not tested in production.
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19.6.2
Flash memory
Table 120. Dual voltage HDFlash memory
Symbol fCPU VPP Parameter Operating frequency Write / Erase mode Programming voltage(2) 4.5V < VDD < 5.5V Run mode (fCPU = 4 MHz) IDD Supply current
(3)
Conditions Read mode
Min(1) 0 1 11.4
Typ
Max(1) 8
Unit MHz
8 12.6 3 mA 0 1 10 A 200 30 10 mA s years cycles 25 85 C V
Write / Erase Power down mode / HALT
IPP tVPP tRET NRW TPROG TERASE
VPP current(3) Internal VPP stabilization time Data retention Write erase cycles Programming or erasing temperature range
Read (VPP = 12V) Write / Erase
TA = 55C TA = 85C
20 100 -40
1. Data based on characterization results, not tested in production 2. VPP must be applied only during the programming or erasing operation and not permanently for reliability reasons. 3. Data based on simulation results, not tested in production
Warning:
Do not connect 12V to VPP before VDD is powered on, as this may damage the device.
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19.7
EMC (electromagnetic compatibility) characteristics
Susceptibility tests are performed on a sample basis during product characterization.
19.7.1
Functional EMS (electromagnetic susceptibility)
Based on a simple running application on the product (toggling two LEDs through I/O ports), the product is stressed by two electromagnetic events until a failure occurs (indicated by the LEDs).
ESD: Electrostatic discharge (positive and negative) is applied on all pins of the device until a functional disturbance occurs. This test conforms with the IEC 1000-4-2 standard. FTB: A burst of fast transient voltage (positive and negative) is applied to VDD and VSS through a 100pF capacitor until a functional disturbance occurs. This test conforms with the IEC 1000-4-4 standard.
A device reset allows normal operations to be resumed. The test results given in Table 121 below are based on the EMS levels and classes defined in application note AN1709.
Designing hardened software to avoid noise problems
EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular. Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for his application. Software recommendations The software flowchart must include the management of runaway conditions such as:

Corrupted program counter Unexpected reset Critical Data corruption (control registers...)
Prequalification trials Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the RESET pin or the oscillator pins for 1 second. To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note AN1015).
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ST72321Bxxx-Auto Table 121. EMS test results
Symbol VFESD Parameter Voltage limits to be applied on any I/O pin to induce a functional disturbance
.
Electrical characteristics
Conditions All Flash and ROM devices, VDD = 5V, TA = +25C, fOSC = 8 MHz, conforms to IEC 1000-4-2 32 Kbyte Flash device LQFP44(1), VDD = 5V, TA = +25C, fOSC = 8 MHz, conforms to IEC 1000-4-4
Level/Class 3B
3B
VFFTB
Fast transient voltage burst limits to be applied through 100pF on VDD and VDD pins to induce a 48/60 Kbyte Flash and all ROM devices, functional disturbance VDD = 5V, TA = +25C, fOSC = 8 MHz, conforms to IEC 1000-4-4
4A
1. VFFTB test results unavailable for LQFP64 32 Kbyte Flash device at this time
19.7.2
EMI (electromagnetic interference)
Based on a simple application running on the product (toggling two LEDs through the I/O ports), the product is monitored in terms of emission. This emission test is in line with the norm SAE J 1752/3 which specifies the board and the loading of each pin.
Table 122. EMI emissions
Conditions Symbol Parameter VDD = 5V, TA = +25C, conforming to SAE J 1752/3 48/60 Kbyte Flash devices in LQFP44 and LQFP64 packages and 32 Kbyte Flash devices in LQFP64 package Monitored frequency band 0.1 MHz to 30 MHz 30 MHz to 130 MHz 130 MHz to 1 GHz SAE EMI Level 0.1 MHz to 30 MHz SEMI Peak level 32 Kbyte Flash devices in LQFP44 package 30 MHz to 130 MHz 130 MHz to 1 GHz SAE EMI Level 48/60 Kbyte ROM devices in LQFP44 and LQFP64 packages and 32 Kbyte ROM devices in LQFP64 package 0.1 MHz to 30 MHz 30 MHz to 130 MHz 130 MHz to 1 GHz SAE EMI Level 0.1 MHz to 30 MHz SEMI Peak level 32 Kbyte ROM devices in LQFP44 package 30 MHz to 130 MHz 130 MHz to 1 GHz SAE EMI Level
1. Data based on characterization results, not tested in production.
Max vs [fOSC/fCPU](1) Unit 8/4 MHz 15 20 7 2.5 13 20 16 3 17 24 18 3 16/8 MHz 20 27 12 3 14 25 21 3.5 11 23 14 3 21 30 23 3.5 dBV dBV dBV dBV
SEMI
Peak level
SEMI
Peak level
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Electrical characteristics
ST72321Bxxx-Auto
19.7.3
Absolute maximum ratings (electrical sensitivity)
Based on two different tests (ESD and LU) using specific measurement methods, the product is stressed in order to determine its performance in terms of electrical sensitivity.
Electrostatic discharge (ESD)
Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts*(n+1) supply pin). This test conforms to the AEC-Q100-002/-003/-011 standard. For more details, refer to the application note AN1181. Table 123. ESD absolute maximum ratings
Symbol VESD(HBM) VESD(MM) VESD(CDM) Ratings Electrostatic discharge voltage (Human Body Model) Electrostatic discharge voltage (Machine Model) Electrostatic discharge voltage (Charged Device Model) Conditions TA = +25C conforming to AEC-Q100-002 TA = +25C conforming to AEC-Q100-003 TA = +25C conforming to AEC-Q100-011 Class H1C M2 C2 Max. value(1) 2000 200 500 V Unit
1. Data based on characterization results, not tested in production.
Static latch-up (LU)
Two complementary static tests are required on six parts to assess the latch-up performance:

A supply overvoltage is applied to each power supply pin. A current injection is applied to each input, output and configurable I/O pin.
These tests are compliant with the EIA/JESD 78 IC latch-up standard. Table 124. Electrical sensitivities
Symbol LU Parameter Static latch-up class Conditions TA = +125C conforming to JESD 78 Class II level A
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ST72321Bxxx-Auto
Electrical characteristics
19.8
19.8.1
I/O port pin characteristics
General characteristics
Subject to general operating conditions for VDD, fOSC, and TA unless otherwise specified.
Table 125. I/O port pin general characteristics
Symbol VIL VIH Vhys IINJ(PIN)(3) Parameter Input low level voltage(1) Input high level voltage
(1)
Conditions
Min
Typ
Max 0.3xVDD
Unit
CMOS ports
0.7xVDD 0.7 0 +4 4 25
V
Schmitt trigger voltage hysteresis(2) Injected current on PC6 pin (Flash devices only) Injected current on an I/O pin VDD = 5V
mA
IINJ(PIN)(3) Ilkg IS RPU CIO tf(IO)out tr(IO)out tw(IT)in
Total injected current (sum of all I/O and control pins) Input leakage current Static current consumption Weak pull-up equivalent resistor(6) I/O pin capacitance Output high to low level fall time(1) time(1) CL = 50pF Between 10% and 90% 1 VSS < VIN < VDD Floating input mode(4)(5) 50 400 120 5 25
1 A 250 k pF ns 25 tCPU
VIN = VSS VDD = 5V
Output low to high level rise
External interrupt pulse time(7)
1. Data based on characterization results, not tested in production. 2. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested. 3. When the current limitation is not possible, the VIN maximum must be respected, otherwise refer to IINJ(PIN) specification. A positive injection is induced by VIN > VDD while a negative injection is induced by VIN < VSS. Refer to Section 19.2.2: Current characteristics for more details. 4. Static peak current value taken at a fixed VIN value, based on design simulation and technology characteristics, not tested in production. This value depends on VDD and temperature values. 5. The Schmitt trigger that is connected to every I/O port is disabled for analog inputs only when ADON bit is ON and the particular ADC channel is selected (with port configured in input floating mode). When the ADON bit is OFF, static current consumption may result. This can be avoided by keeping the input voltage of this pin close to VDD or VSS. 6. The RPU pull-up equivalent resistor is based on a resistive transistor (corresponding IPU current characteristics described in Figure 80). 7. To generate an external interrupt, a minimum pulse width has to be applied on an I/O port pin configured as an external interrupt source.
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Electrical characteristics
ST72321Bxxx-Auto
Figure 79. Unused I/O pins configured as input
Figure 80. Typical IPU vs VDD with VIN = VSS
90
VDD 10k
ST7XXX
80 70
Ta=1 40C Ta=9 5C Ta=2 5C Ta=-45 C
UNUSED I/O PORT
Ipu(uA)
60 50 40 30 20
UNUSED I/O PORT 10k
ST7XXX
Note: I/O can be left unconnected if it is configured as output (0 or 1) by the software. This has the advantage of greater EMC robustness and lower cost.
10 0 2 2.5 3 3.5 4 4.5 Vdd(V) 5 5.5 6
19.8.2
Output driving current
Subject to general operating conditions for VDD, fCPU, and TA unless otherwise specified.
Table 126. Output driving current
Symbol Parameter Output low level voltage for a standard I/O pin when 8 pins are sunk at same time (see Figure 81) VOL(1) Output low level voltage for a high sink I/O pin when 4 pins are sunk at same time (see Figure 82 and Figure 84) Conditions IIO = +5mA IIO = +2mA IIO = +20mA, TA < 85C TA > 85C IIO = +8mA Output high level voltage for an I/O pin when 4 pins are sourced at same time (see Figure 83 and Figure 86) IIO = -5mA, TA < 85C TA > 85C IIO = -2mA VDD - 1.4 VDD - 1.6 VDD - 0.7 Min Max 1.2 0.5 Unit
VDD = 5V
1.3 1.5 0.6
V
VOH(2)
1. The IIO current sunk must always respect the absolute maximum rating specified in Section 19.2.2 and the sum of IIO (I/O ports and control pins) must not exceed IVSS. 2. The IIO current sourced must always respect the absolute maximum rating specified in Section 19.2.2 and the sum of IIO (I/O ports and control pins) must not exceed IVDD. True open-drain I/O pins do not have VOH.
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ST72321Bxxx-Auto
Electrical characteristics
Figure 81. Typical VOL at VDD = 5V (standard)
1.4 1.2
Figure 82. Typical VOL at VDD = 5V (high-sink)
1 0.9 0.8 V ol(V ) at Vdd=5V 0.7 0.6 0.5 0.4
Ta= 140 C
V ol (V ) at Vdd=5V
1 0.8 0.6 0.4 0.2 0 0 0.005 Iio(A) 0.01 0.015
Ta =14 0C " Ta =95 C Ta =25 C Ta =-45 C
0.3 0.2 0.1 0
0 0.01 0.02 Iio(A)
Ta= 95 C Ta= 25 C Ta= -45C
0.03
Figure 83. Typical VOH at VDD = 5V
5.5 5 Vdd-V oh (V ) at Vdd=5V 4.5 4 3.5
V dd= 5V 1 40C m in
3 2.5 2 -0.01
V dd= 5v 95C m in V dd= 5v 25C m in V dd= 5v -4 5C m in
-0.008 -0.006 -0.004 Iio (A)
-0.002
0
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Electrical characteristics Figure 84. Typical VOL versus VDD (standard)
1
Ta= -4 5C
ST72321Bxxx-Auto
0.45
Ta=-4 5C
Ta= 25C Ta= 95C Ta= 140 C
0.9 0.8 V ol(V ) at Iio=5m A 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 2 2.5 3 3.5 4 Vdd(V ) 4.5
0.4 0.35 Vol(V) at Iio=2mA 0.3 0.25 0.2 0.15 0.1 0.05
Ta=2 5C Ta=9 5C Ta=1 40C
5
5.5
6
0 2 2.5 3 3.5 4 Vdd(V) 4.5 5 5.5 6
Figure 85. Typical VOL versus VDD (high-sink)
0 .6
1 .6
1 .4
0 .5
Ta = 140 C Ta =95 C
1 .2
0 .4
Ta =25 C Ta =-45C
Vol(V ) at Iio=20m A
Vol(V ) at Iio=8m A
1
0 .3
0 .8
0 .6
0 .2
Ta= 14 0C Ta=9 5C
0 .4
0 .1
Ta=2 5C
0 .2
Ta=-45 C
0 2 2.5 3 3.5 4 V dd (V ) 4.5 5 5.5 6
0 2 2.5 3 3.5 4 V dd(V ) 4.5 5 5.5 6
Figure 86. Typical VDD-VOH versus VDD
5.5 5 Vdd-V oh(V ) at Iio=-2m A 4.5 4 3.5
Ta= -4 5C
6
Ta= -4 5C
5 Vdd-Voh(V) at Iio=-5mA
Ta= 25C Ta= 95C
4
Ta= 140C
3
3 2.5
Ta= 25C Ta= 95C
2
1
Ta= 140C
2 2 2.5 3 3.5 4 Vdd(V) 4.5 5 5.5 6
0 2 2.5 3 3.5 4 Vdd(V) 4.5 5 5.5 6
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ST72321Bxxx-Auto
Electrical characteristics
19.9
19.9.1
Control pin characteristics
Asynchronous RESET pin
Subject to general operating conditions for VDD, fCPU, and TA unless otherwise specified.
Table 127. Asynchronous RESET pin characteristics
Symbol VIL VIH Vhys VOL IIO RON Parameter Input low level voltage(1) Input high level voltage Schmitt trigger voltage hysteresis(2) Output low level voltage(3) Input current on RESET pin Weak pull-up equivalent resistor Stretch applied on external pulse tw(RSTL)out Generated reset pulse duration th(RSTL)in tg(RSTL)in External reset pulse hold Filtered glitch duration(6) time(5) Internal reset sources 20 0 20 2.5 200 ns 30 VDD = 5V, IIO = +2mA
(1)
Conditions
Min
Typ
Max 0.3xVDD
Unit
0.7xVDD V 2.5 0.2 2 30 120 42(4) 42(4) s 0.5 mA k
1. Data based on characterization results, not tested in production. 2. Hysteresis voltage between Schmitt trigger switching levels. 3. The IIO current sunk must always respect the absolute maximum rating specified in Section 19.2.2 and the sum of IIO (I/O ports and control pins) must not exceed IVSS. 4. Data guaranteed by design, not tested in production. 5. To guarantee the reset of the device, a minimum pulse has to be applied to the RESET pin. All short pulses applied on the RESET pin with a duration below th(RSTL)in can be ignored. 6. The reset network (the resistor and two capacitors) protects the device against parasitic resets, especially in noisy environments.
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Electrical characteristics Figure 87. RESET pin protection when LVD is enabled
VDD
ST72321Bxxx-Auto
ST72XXX
Required
EXTERNAL RESET
0.01F
Optional (note 3)
RON
Filter
INTERNAL RESET
1M
PULSE GENERATOR
WATCHDOG LVD RESET
Note:
1
- The reset network protects the device against parasitic resets. - The output of the external reset circuit must have an open-drain output to drive the ST7 reset pad. Otherwise the device can be damaged when the ST7 generates an internal reset (LVD or watchdog). - Whether the reset source is internal or external, the user must ensure that the level on the RESET pin can go below the VIL maximum level specified in Section 19.9.1 on page 211. Otherwise the reset will not be taken into account internally. - Because the reset circuit is designed to allow the internal RESET to be output in the RESET pin, the user must ensure that the current sunk on the RESET pin is less than the absolute maximum value specified for IINJ(RESET) in Section 19.2.2 on page 192. When the LVD is enabled, it is recommended not to connect a pull-up resistor or capacitor. A 10nF pull-down capacitor is required to filter noise on the reset line. In case a capacitive power supply is used, it is recommended to connect a 1M pull-down resistor to the RESET pin to discharge any residual voltage induced by the capacitive effect of the power supply (this will add 5A to the power consumption of the MCU). Tips when using the LVD: A. Check that all recommendations related to reset circuit have been applied (see notes above). B. Check that the power supply is properly decoupled (100nF + 10F close to the MCU). Refer to AN1709 and AN2017. If this cannot be done, it is recommended to put a 100nF + 1M pull-down on the RESET pin. C. The capacitors connected on the RESET pin and also the power supply are key to avoid any start-up marginality. In most cases, steps A and B above are sufficient for a robust solution. Otherwise, replace 10nF pull-down on the RESET pin with a 5F to 20F capacitor.
2 3
4
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ST72321Bxxx-Auto Figure 88. RESET pin protection when LVD is disabled
Electrical characteristics
VDD
ST72XXX
RON
USER EXTERNAL RESET CIRCUIT 0.01F
Filter
INTERNAL RESET
PULSE GENERATOR
Required
WATCHDOG
Note:
- The reset network protects the device against parasitic resets. - The output of the external reset circuit must have an open-drain output to drive the ST7 reset pad. Otherwise the device can be damaged when the ST7 generates an internal reset (LVD or watchdog). - Whether the reset source is internal or external, the user must ensure that the level on the RESET pin can go below the VIL maximum level specified in Section 19.9.1 on page 211. Otherwise the reset will not be taken into account internally. - Because the reset circuit is designed to allow the internal RESET to be output in the RESET pin, the user must ensure that the current sunk on the RESET pin is less than the absolute maximum value specified for IINJ(RESET) in Section 19.2.2 on page 192.
19.9.2
ICCSEL/VPP pin
Subject to general operating conditions for VDD, fCPU, and TA unless otherwise specified. Table 128. ICCSEL/VPP pin characteristics
Symbol VIL VIH Ilkg Parameter Input low level voltage(1) Input high level voltage Input leakage current
(1)
Conditions
Min VSS 0.7 x VDD
Max(1) 0.3 x VDD VDD 1
Unit V A
VIN = VSS
1. Data based on design simulation and/or technology characteristics, not tested in production
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Electrical characteristics Figure 89. Two typical applications with ICCSEL/VPP pin(1)
ST72321Bxxx-Auto
ICCSEL/VPP
PROGRAMMING TOOL 10k
VPP
ST72XXX
ST72XXX
1. When ICC mode is not required by the application, the ICCSEL/VPP pin must be tied to VSS.
19.10
Timer peripheral characteristics
Subject to general operating conditions for VDD, fOSC, and TA unless otherwise specified. Refer to Section 19.8: I/O port pin characteristics for more details on the input/output alternate function characteristics (such as output compare, input capture, external clock, or PWM output). Table 129. 8-bit PWM-ART auto-reload timer characteristics
Symbol Parameter Conditions Min 1 tres(PWM) PWM resolution time fEXT fPWM ART external clock frequency 0 PWM repetition rate fCPU/2 8 VDD = 5V, Resolution = 8 bits 20 MHz bit mV fCPU = 8 MHz 125 Typ Max Unit tCPU ns
ResPWM PWM resolution VOS PWM/DAC output step voltage
Table 130. 16-bit timer characteristics
Symbol Parameter Conditions Min 1 2 tres(PWM) PWM resolution time fEXT fPWM Timer external clock frequency 0 PWM repetition rate fCPU/4 16 MHz bit fCPU = 8 MHz 250 Typ Max Unit tCPU tCPU ns
tw(ICAP)in Input capture pulse time
ResPWM PWM resolution
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ST72321Bxxx-Auto
Electrical characteristics
19.11
19.11.1
Communication interface characteristics
SPI (serial peripheral interface)
Subject to general operating conditions for VDD, fCPU, and TA unless otherwise specified. Refer to Section 19.8: I/O port pin characteristics for more details on the input/output alternate function characteristics (SS, SCK, MOSI, MISO).
Table 131. SPI characteristics
Symbol fSCK 1/tc(SCK) tr(SCK) tf(SCK) tsu(SS)(1) th(SS)(1) Parameter SPI clock frequency Conditions Master, fCPU = 8 MHz Slave, fCPU = 8 MHz SPI clock rise and fall time SS setup time(2) SS hold time Slave Slave Master Slave Master Slave Master Slave Slave Slave Slave (after enable edge) Data output hold time Data output valid time Master (after enable edge) Data output hold time 0 0 120 tCPU Min fCPU/128 = 0.0625 0 Max fCPU/4 = 2 fCPU/2 = 4 Unit MHz
see I/O port pin description tCPU + 50 120 100 90 100 100 100 100 0 120 240 120 ns
tw(SCKH)(1) SCK high and low time tw(SCKL)(1) tsu(MI)(1) tsu(SI)(1) th(MI)(1) th(SI)(1) ta(SO)(1) tdis(SO)(1) tv(SO)
(1) (1)
Data input setup time Data input hold time Data output access time Data output disable time Data output valid time
th(SO)
tv(MO)(1) th(MO)
(1)
1. Data based on design simulation and/or characterization results, not tested in production. 2. Depends on fCPU. For example, if fCPU = 8 MHz, then tCPU = 1 / fCPU = 125 ns and tsu(SS) = 175 ns.
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Electrical characteristics Figure 90. SPI slave timing diagram with CPHA = 0(1)
SS INPUT tsu(SS) SCK INPUT CPHA=0 CPOL=0 CPHA=0 CPOL=1 ta(SO) MISO OUTPUT tw(SCKH) tw(SCKL) tv(SO) th(SO) tr(SCK) tf(SCK) tc(SCK)
ST72321Bxxx-Auto
th(SS)
tdis(SO)
See note 2
See note 2
MSB OUT
BIT6 OUT
LSB OUT
tsu(SI)
th(SI)
MOSI INPUT
MSB IN
BIT1 IN
LSB IN
1. Measurement points are done at CMOS levels: 0.3xVDD and 0.7xVDD. 2. When no communication is on-going the data output line of the SPI (MOSI in master mode, MISO in slave mode) has its alternate function capability released. In this case, the pin status depends on the I/O port configuration.
Figure 91. SPI slave timing diagram with CPHA = 1(1)
SS INPUT tsu(SS) SCK INPUT CPHA=1 CPOL=0 CPHA=1 CPOL=1 ta(SO) tw(SCKH) tw(SCKL) tv(SO) th(SO) tr(SCK) tf(SCK)
LSB OUT
tc(SCK)
th(SS)
tdis(SO)
MISO OUTPUT
See note 2
HZ
MSB OUT
BIT6 OUT
See note 2
tsu(SI)
th(SI)
MOSI INPUT
MSB IN
BIT1 IN
LSB IN
1. Measurement points are done at CMOS levels: 0.3xVDD and 0.7xVDD. 2. When no communication is on-going the data output line of the SPI (MOSI in master mode, MISO in slave mode) has its alternate function capability released. In this case, the pin status depends of the I/O port configuration.
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ST72321Bxxx-Auto Figure 92. SPI master timing diagram(1)
SS INPUT tc(SCK) CPHA = 0 CPOL = 0 SCK INPUT CPHA = 0 CPOL = 1 CPHA = 1 CPOL = 0 CPHA = 1 CPOL = 1 tw(SCKH) tw(SCKL) tsu(MI) MISO INPUT th(MI)
Electrical characteristics
tr(SCK) tf(SCK)
MSB IN
BIT6 IN
LSB IN
tv(MO)
th(MO)
MOSI OUTPUT
See note 2
MSB OUT
BIT6 OUT
LSB OUT
See note 2
1. Measurement points are done at CMOS levels: 0.3xVDD and 0.7xVDD. 2. When no communication is on-going the data output line of the SPI (MOSI in master mode, MISO in slave mode) has its alternate function capability released. In this case, the pin status depends of the I/O port configuration.
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Electrical characteristics
ST72321Bxxx-Auto
19.11.2
I2C - inter IC control interface
Subject to general operating conditions for VDD, fCPU, and TA unless otherwise specified. Refer to Section 19.8: I/O port pin characteristics for more details on the input/output alternate function characteristics (SDAI and SCLI). The ST7 I2C interface meets the requirements of the standard I2C communication protocol described in the following table.
Table 132. I2C control interface characteristics
Standard mode I2C Symbol tw(SCLL) tw(SCLH) tsu(SDA) th(SDA) tr(SDA) tr(SCL) tf(SDA) tf(SCL) th(STA) tsu(STA) tsu(STO) Parameter SCL clock low time SCL clock high time SDA setup time SDA data hold time SDA and SCL rise time SDA and SCL fall time START condition hold time Repeated START condition setup time STOP condition setup time 4.0 4.7 4.0 4.7 400 1.3 400 pF 0.6 s Min(2) 4.7 4.0 250 0(3) 1000 20+0.1Cb 300 300 Max(2) Fast mode I2C(1) Min(2) 1.3 s 0.6 100 0(4) 900(3) ns Max(2) Unit
tw(STO:STA) STOP to START condition time (bus free) Cb Capacitive load for each bus line
1. At 4 MHz fCPU, maximum I2C speed (400 kHz) is not achievable. In this case, maximum I2C speed will be approximately 260 kHz. 2. Data based on standard I2C protocol requirement, not tested in production. 3. The maximum hold time of the START condition has only to be met if the interface does not stretch the low period of SCL signal. 4. The device must internally provide a hold time of at least 300ns for the SDA signal in order to bridge the undefined region of the falling edge of SCL.
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ST72321Bxxx-Auto Figure 93. Typical application with I2C BUS and timing diagram(1)
VDD 4.7k I2C BUS 4.7k VDD 100 100 SDAI SCLI
Electrical characteristics
ST72XXX
REPEATED START START
tsu(STA)
SDA
tw(STO:STA)
START
tf(SDA)
SCK
tr(SDA)
tsu(SDA)
th(SDA)
STOP
th(STA)
tw(SCKH)
tw(SCKL)
tr(SCK)
tf(SCK)
tsu(STO)
1. Measurement points are done at CMOS levels: 0.3xVDD and 0.7xVDD.
The following table provides the values to be written in the I2CCCR register to obtain the required I2C SCL line frequency. Table 133. SCL frequency table
I2CCCR value fSCL (kHz) VDD = 4.1V fCPU = 4 MHz VDD = 5V VDD = 4.1V fCPU = 8 MHz VDD = 5V
RP = 3.3k RP = 4.7k RP = 3.3k RP = 4.7k RP = 3.3k RP = 4.7k RP = 3.3k RP = 4.7k 400 300 200 100 50 20 Not achievable Not achievable 83h 10h 24h 5Fh 8Ah 24h 89h 23h 4Ch FFh 24h 83h 85h 8Ah 23h
Legend: RP Note: = External pull-up resistance fSCL = I2C speed - For speeds around 200 kHz, the achieved speed can have a 5% tolerance. - For other speed ranges, the achieved speed can have a 2% tolerance. The above variations depend on the accuracy of the external components used.
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Electrical characteristics
ST72321Bxxx-Auto
19.12
10-bit ADC characteristics
Subject to general operating conditions for VDD, fCPU, and TA unless otherwise specified.
Table 134. 10-bit ADC characteristics
Symbol fADC VAREF VAIN Ilkg RAIN CAIN fAIN CADC tADC Parameter ADC clock frequency Analog reference voltage Conversion voltage range(1) Input leakage current for analog input(2) External input impedance External capacitor on analog input Variation frequency of analog input signal Internal sample and hold capacitor Conversion time (Sample + Hold) fCPU = 8 MHz, speed = 0, fADC = 2 MHz No. of sample capacitor loading cycles No. of hold conversion cycles 12 7.5 -40C < TA < 85C range Other TA ranges 0.7*VDD < VAREF < VDD Conditions Min 0.4 3.8 VSSA Typ Max 2 VDD VAREF 250 1 See Figure 94 and Figure 95 nA A k pF Hz pF s Unit MHz V
4 1/fADC 11
tADC
1. Any added external serial resistor will downgrade the ADC accuracy (especially for resistance greater than 10k). Data based on characterization results, not tested in production. 2. Injecting negative current on adjacent pins may result in increased leakage currents. Software filtering of the converted analog value is recommended.
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ST72321Bxxx-Auto
Electrical characteristics
Figure 94. RAIN maximum versus fADC with CAIN = 0pF(1)
Figure 95. Recommended CAIN and RAIN values(1)
45 40
1000
Cain 10 nF
Max. R AIN (Kohm)
35 30 25 20 15 10 5 0 0 10 30
2 MHz
100
Cain 22 nF Cain 47 nF
1 MHz
Max. R AIN (Kohm)
10
1
0.1
70
0.01
0.1
1
10
CPARASITIC (pF)
fAIN(KHz)
1. CPARASITIC represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad capacitance (3pF). A high CPARASITIC value will downgrade conversion accuracy. To remedy this, fADC should be reduced.
1. This graph shows that, depending on the input signal variation (fAIN), CAIN can be increased for stabilization time and decreased to allow the use of a larger serial resistor (RAIN).
Figure 96. Typical A/D converter application
VDD VT 0.6V
ST72XXX
2k(max)
RAIN VAIN CAIN
AINx
10-bit A/D conversion CADC 12pF
VT 0.6V
Ilkg
19.12.1
Analog power supply and reference pins
Depending on the MCU pin count, the package may feature separate VAREF and VSSA analog power supply pins. These pins supply power to the A/D converter cell and function as the high and low reference voltages for the conversion. Separation of the digital and analog power pins allow board designers to improve A/D performance. Conversion accuracy can be impacted by voltage drops and noise in the event of heavily loaded or badly decoupled power supply lines (see Section 19.12.2: General PCB design guidelines).
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Electrical characteristics
ST72321Bxxx-Auto
19.12.2
General PCB design guidelines
To obtain best results, some general design and layout rules should be followed when designing the application PCB to shield the noise-sensitive, analog physical interface from noise-generating CMOS logic signals.

Use separate digital and analog planes. The analog ground plane should be connected to the digital ground plane via a single point on the PCB. Filter power to the analog power planes. It is recommended to connect capacitors, with good high frequency characteristics, between the power and ground lines, placing 0.1F and optionally, if needed 10pF capacitors as close as possible to the ST7 power supply pins and a 1 to 10F capacitor close to the power source (see Figure 97). The analog and digital power supplies should be connected in a star network. Do not use a resistor, as VAREF is used as a reference voltage by the A/D converter and any resistance would cause a voltage drop and a loss of accuracy. Properly place components and route the signal traces on the PCB to shield the analog inputs. Analog signals paths should run over the analog ground plane and be as short as possible. Isolate analog signals from digital signals that may switch while the analog inputs are being sampled by the A/D converter. Do not toggle digital outputs on the same I/O port as the A/D input being converted.
Figure 97. Power supply filtering
ST72XXX 1 to 10F
ST7 DIGITAL NOISE FILTERING
0.1F
VSS
+
VDD
VDD
POWER SUPPLY SOURCE EXTERNAL NOISE FILTERING
0.1F
VAREF
VSSA
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ST72321Bxxx-Auto
Electrical characteristics
19.12.3
ADC accuracy
Figure 98. ADC error classification
Digital Result ADCDR 1023 1022 1021 V -V AREF SSA 1LSB = -------------------------------------------IDEAL 1024 (2) ET 7 6 5 4 3 2 1 0 VSSA 1 2 3 4 1 LSBIDEAL Vin (LSBIDEAL) 5 6 7 1021 1022 1023 1024 VAREF EO EL (3) (1) EG Legend: (1) Example of an actual transfer curve (2) The ideal transfer curve (3) End point correlation line ET = Total Unadjusted Error: maximum deviation between the actual and the ideal transfer curves. EO = Offset Error: deviation between the first actual transition and the first ideal one. EG = Gain Error: deviation between the last ideal transition and the last actual one. ED = Differential Linearity Error: maximum deviation between actual steps and the ideal one. ED EL = Integral Linearity Error: maximum deviation between any actual transition and the end point correlation line.
Table 135. ADC accuracy
Max(2) Symbol Parameter(1) Conditions Typ ROM and 48/60 Kbyte Flash 4 3 3 2 3 32 Kbyte Flash 6 5 4.5 2 1 Integral linearity error LSB Unit
|ET| |EO| |EG| |ED| |EL|
Total unadjusted error Offset error Gain error Differential linearity error VDD = 5V(1) CPU in run mode @ fADC 2 MHz
3 2 0.5
1. ADC Accuracy versus Negative Injection Current: Injecting negative current may reduce the accuracy of the conversion being performed on another analog input. Any positive injection current within the limits specified for IINJ(PIN) and IINJ(PIN) in Section 19.8 does not affect the ADC accuracy. 2. Data based on characterization results, monitored in production to guarantee 99.73% within max value from -40C to 125C ( 3 distribution limits).
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Package characteristics
ST72321Bxxx-Auto
20
20.1
Package characteristics
Package mechanical data
Figure 99. 64-pin (14x14) low profile quad flat package outline
D D1 A1 A A2
b
e E1 E
L L1 c
Table 136. 64-pin (14x14) low profile quad flat package mechanical data
mm Dimension Min A A1 A2 b c D D1 E E1 e L L1 0 0.450 0.050 1.350 0.300 0.090 16.000 14.000 16.000 14.000 0.800 3.5 0.600 1.000 7 0.750 0 0.0177 1.400 0.370 Typ Max 1.600 0.150 1.450 0.450 0.200 0.0020 0.0531 0.0118 0.0035 0.6299 0.5512 0.6299 0.5512 0.0315 3.5 0.0236 0.0394 7 0.0295 0.0551 0.0146 Min Typ Max 0.0630 0.0059 0.0571 0.0177 0.0079 inches(1)
1. Values in inches are converted from mm and rounded to 4 decimal digits.
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Package characteristics
Figure 100. 64-pin (10x10) low profile quad flat package outline
D D1 A1
A A2
b
E1 E e
L L1
c
Table 137. 64-pin (10x10) low profile quad flat package mechanical data
mm Dimension Min A A1 A2 b c D D1 E E1 e L L1 0 0.450 0.050 1.350 0.170 0.090 12.000 10.000 12.000 10.000 0.500 3.5 0.600 1.000 7 0.750 0 0.0177 1.400 0.220 Typ Max 1.600 0.150 1.450 0.270 0.200 0.0020 0.0531 0.0067 0.0035 0.4724 0.3937 0.4724 0.3937 0.0197 3.5 0.0236 0.0394 7 0.0295 0.0551 0.0087 Min Typ Max 0.0630 0.0059 0.0571 0.0106 0.0079 inches(1)
1. Values in inches are converted from mm and rounded to 4 decimal digits.
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Package characteristics Figure 101. 44-pin (10x10) low profile quad flat package outline
D D1 A1
ST72321Bxxx-Auto
A A2
b
E1
E
e
L1 L
c
Table 138. 44-pin (10x10) low profile quad flat package mechanical data
mm Dimension Min A A1 A2 b C D D1 E E1 e L L1 0 0.450 0.050 1.350 0.300 0.090 12.000 10.000 12.000 10.000 0.800 3.5 0.600 1.000 7 0.750 0 0.0177 1.400 0.370 Typ Max 1.600 0.150 1.450 0.450 0.200 0.0020 0.0531 0.0118 0.0035 0.4724 0.3937 0.4724 0.3937 0.0315 3.5 0.0236 0.0394 7 0.0295 0.0551 0.0146 Min Typ Max 0.0630 0.0059 0.0571 0.0177 0.0079 inches(1)
1. Values in inches are converted from mm and rounded to 4 decimal digits.
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Package characteristics
20.2
Thermal characteristics
Table 139. Thermal characteristics
Symbol Ratings Package thermal resistance (junction to ambient) LQFP64 14x14 LQFP64 10x10 LQFP44 10x10 Power dissipation(1) Maximum junction temperature(2) Value Unit
RthJA
47 50 52 500 150
C/W
PD TJmax
mW C
1. The maximum power dissipation is obtained from the formula PD = (TJ -TA) / RthJA. The power dissipation of an application can be defined by the user with the formula: PD = PINT + PPORT where PINT is the chip internal power (IDD x VDD) and PPORT is the port power dissipation depending on the ports used in the application. 2. The maximum chip-junction temperature is based on technology characteristics.
20.3
Soldering information
In accordance with the RoHS European directive, all STMicroelectronics packages have been converted to lead-free technology, named ECOPACK(R).

ECOPACK(R) packages are qualified according to the JEDEC STD-020B compliant soldering profile. Detailed information on the STMicroelectronics ECOPACK(R) transition program is available on www.st.com/stonline/leadfree/, with specific technical application notes covering the main technical aspects related to lead-free conversion (AN2033, AN2034, AN2035 and AN2036).
20.3.1
Compatibility
ECOPACK(R) LQFP packages are fully compatible with lead (Pb) containing soldering process (see application note AN2034). Table 140. Soldering compatibility (wave and reflow soldering process)
Package LQFP Plating material Sn (pure tin) Pb solder paste Yes Pb-free solder paste Yes
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Device configuration and ordering information
ST72321Bxxx-Auto
21
Device configuration and ordering information
Each device is available for production in user programmable versions (Flash) as well as in factory coded versions (ROM/FASTROM). ST72321B-Auto devices are ROM versions. ST72P321B-Auto devices are Factory Advanced Service Technique ROM (FASTROM) versions: They are factory-programmed HDFlash devices. Flash devices are shipped to customers with a default content, whereas ROM/FASTROM factory coded parts contain the code supplied by the customer. This implies that Flash devices have to be configured by the customer using the option bytes while the ROM/FASTROM devices are factory-configured. Detailed device configuration and ordering information is presented in the following Section 21.1: Flash devices and Section 21.2: ROM device ordering information and transfer of customer code.
21.1
21.1.1
Flash devices
Flash configuration
Table 141. Flash option bytes
Static option byte 0
7 WDG Res HALT SW 1 1 1 0 0 0 1 1 6 5 4 VD Reserved 3 2 1 0 FMP_R 7 PKG1 6 RSTC
Static option byte 1
5 4 3 2 1 0 PLLOFF 1
OSCTYPE 1 1 0 0
OSCRANGE 2 0 1 1 0 1
Default value:
1
1
(1)
1
1. Depends on device type as defined in Table 144: Package selection (OPT7) on page 230
The option bytes allow the hardware configuration of the microcontroller to be selected. They have no address in the memory map and can be accessed only in programming mode (for example, using a standard ST7 programming tool). The default content of the Flash is fixed to FFh. To program the Flash devices directly using ICP, Flash devices are shipped to customers with the internal RC clock source enabled. In masked ROM devices, the option bytes are fixed in hardware by the ROM code (see option list). Table 142. Option byte 0 bit description
Bit Name Function Watchdog and Halt mode This option bit determines if a RESET is generated when entering Halt mode while the Watchdog is active. 0: No Reset generation when entering Halt mode 1: Reset generation when entering Halt mode
OPT7
WDG HALT
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Device configuration and ordering information
Table 142. Option byte 0 bit description (continued)
Bit Name Function Hardware or software watchdog This option bit selects the watchdog type. 0: Hardware (watchdog always enabled) 1: Software (watchdog to be enabled by software) Reserved, must be kept at default value. Voltage detection These option bits enable the voltage detection block (LVD and AVD) with a selected threshold for the LVD and AVD (EVD + AVD). 00: Selected LVD = Highest threshold (VDD~4V) 01: Selected LVD = Medium threshold (VDD~3.5V) 10: Selected LVD = Lowest threshold (VDD~3V) 11: LVD and AVD off Caution: If the medium or low thresholds are selected, the detection may occur outside the specified operating voltage range. Below 3.8V, device operation is not guaranteed. For details on the AVD and LVD threshold levels refer to Section 19.3.2: Operating conditions with low voltage detector (LVD) on page 194. Reserved, must be kept at default value Flash memory readout protection Readout protection, when selected, provides a protection against program memory content extraction and against write access to Flash memory. Erasing the option bytes when the FMP_R option is selected causes the whole user memory to be erased first, after which the device can be reprogrammed. Refer to Section 4.3.1: Readout protection on page 37 and the ST7 Flash Programming Reference Manual for more details. 0: Readout protection enabled 1: Readout protection disabled
OPT6
WDG SW
OPT5
-
OPT4:3
VD[1:0]
OPT2:1
-
OPT0
FMP_R
Table 143. Option byte 1 bit description
Bit Name Function Package selection bit 1 This option bit selects the package (see Table 144: Package selection (OPT7)). RESET clock cycle selection This option bit selects the number of CPU cycles applied during the RESET phase and when exiting Halt mode. For resonator oscillators, it is advised to select 4096 due to the long crystal stabilization time. 0: Reset phase with 4096 CPU cycles 1: Reset phase with 256 CPU cycles Oscillator type These option bits select the ST7 main clock source type. 00: Clock source = Resonator oscillator 01: Reserved 10: Clock source = Internal RC oscillator 11: Clock source = External source
OPT7
PKG1
OPT6
RSTC
OPT5:4
OSCTYPE[1:0]
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Device configuration and ordering information Table 143. Option byte 1 bit description (continued)
Bit Name Function
ST72321Bxxx-Auto
Oscillator range When the resonator oscillator type is selected, these option bits select the resonator oscillator current source corresponding to the frequency range of the resonator used. When the external clock source is OPT3:1 OSCRANGE[2:0] selected, these bits are set to medium power (2 ~ 4 MHz). 000: Typ. frequency range = 1 ~ 2 MHz 001: Typ. frequency range = 2 ~ 4 MHz 010: Typ. frequency range = 4 ~ 8 MHz 011: Typ. frequency range = 8 ~ 16 MHz PLL activation This option bit activates the PLL which allows multiplication by two of the main input clock frequency. The PLL is guaranteed only with an input frequency between 2 and 4 MHz. For this reason the PLL must not be used with the internal RC oscillator. 0: PLL x2 enabled 1: PLL x2 disabled Caution: The PLL can be enabled only if the OSCRANGE (OPT3:1) bits are configured to 2 ~ 4 MHz. Otherwise, the device functionality is not guaranteed.
OPT0
PLLOFF
Table 144. Package selection (OPT7)
Version R/AR J Selected package LQFP64 LQFP44 32 Kbytes 1 Flash size 32/48/60 Kbytes 48/60 Kbytes PKG1 1 0
Note:
On the chip, each I/O port has up to eight pads. Pads that are not bonded to external pins are in input pull-up configuration after reset. The configuration of these pads must be kept at reset state to avoid added current consumption.
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Device configuration and ordering information
21.1.2
Flash ordering information
The following Table 145 serves as a guide for ordering. Table 145. Flash user programmable device types
Order code(1) ST72F321BJ6TARE ST72F321BJ7TARE ST72F321BJ9TARE ST72F321BAR6TARE ST72F321BAR7TARE ST72F321BAR9TARE ST72F321BR6TARE ST72F321BR7TARE ST72F321BR9TARE ST72F321BJ6TCRE ST72F321BJ7TCRE ST72F321BJ9TCRE ST72F321BAR6TCRE ST72F321BAR7TCRE ST72F321BAR9TCRE ST72F321BR6TCRE ST72F321BR7TCRE ST72F321BR9TCRE
1. R = Tape and Reel (left blank if Tray)
Package
Memory (Kbytes) 32
Temperature range
LQFP44 (10 x 10)
48 60 32
LQFP64 (10 x 10)
48 60 32
-40C to +85C
LQFP64 (14 x 14)
48 60 32
LQFP44 (10 x 10)
48 60 32
LQFP64 (10 x 10)
48 60 32
-40C to +125C
LQFP64 (14 x 14)
48 60
Figure 102. Flash commercial product code structure
DEVICE PINOUT PROG MEM PACKAGE TEMP RANGE R E
E = Lead-free (ECOPACK(R)) Conditioning options: R = Tape and Reel (left blank if Tray) A = -40 to +85C C = -40 to +125C T = Low profile quad flat pack 6 = 32 Kbytes 7 = 48 Kbytes 9 = 60 Kbytes J = 44 pins AR = 64 pins (10x10) R = 64 pins (14x14) ST72F321B
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Device configuration and ordering information
ST72321Bxxx-Auto
21.2
ROM device ordering information and transfer of customer code
Customer code is made up of the ROM/FASTROM contents and the list of the selected options (if any). The ROM/FASTROM contents are to be sent on diskette, or by electronic means, with the S19 hexadecimal file generated by the development tool. All unused bytes must be set to FFh. Complete the appended ST72321B-Auto MIcrocontroller FASTROM/ROM Option List on page 236 to communicate the selected options to STMicroelectronics and check for regular updates of the option list on the ST website or ask your ST representative. Refer to application note AN1635 for information on the counter listing returned by ST after code has been transferred. The following Table 146: FASTROM factory coded device types and Table 147: ROM factory coded device types on page 234 serve as guides for ordering. The STMicroelectronics Sales Organization will be pleased to provide detailed information on contractual points.
Caution:
The Readout Protection binary value is inverted between ROM and Flash products. The option byte checksum will differ between ROM and Flash. Table 146. FASTROM factory coded device types
Order code(1) ST72P321B(J6)TAxxxRE ST72P321B(J7)TAxxxRE ST72P321B(J9)TAxxxRE ST72P321B(AR6)TAxxxRE ST72P321B(AR7)TAxxxRE ST72P321B(AR9)TAxxxRE ST72P321B(R6)TAxxxRE ST72P321B(R7)TAxxxRE ST72P321B(R9)TAxxxRE ST72P321B(J6)TBxxxRE ST72P321B(J7)TBxxxRE ST72P321B(J9)TBxxxRE ST72P321B(AR6)TBxxxRE ST72P321B(AR7)TBxxxRE ST72P321B(AR9)TBxxxRE ST72P321B(R6)TBxxxRE ST72P321B(R7)TBxxxRE ST72P321B(R9)TBxxxRE LQFP64 (14 x 14) LQFP64 (10 x 10) LQFP44 (10 x 10) LQFP64 (14 x 14) LQFP64 (10 x 10) LQFP44 (10 x 10) Package Memory (Kbytes) 32 48 60 32 48 60 32 48 60 32 48 60 32 48 60 32 48 60 -40C to +105C -40C to +85C Temperature range
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Device configuration and ordering information
Table 146. FASTROM factory coded device types (continued)
Order code(1) ST72P321B(J6)TCxxxRE ST72P321B(J7)TCxxxRE ST72P321B(J9)TCxxxRE ST72P321B(AR6)TCxxxRE ST72P321B(AR7)TCxxxRE ST72P321B(AR9)TCxxxRE ST72P321B(R6)TCxxxRE ST72P321B(R7)TCxxxRE ST72P321B(R9)TCxxxRE LQFP64 (14 x 14) LQFP64 (10 x 10) LQFP44 (10 x 10) Package Memory (Kbytes) 32 48 60 32 48 60 32 48 60 -40C to +125C Temperature range
1. - The two or three characters in parentheses which represent the pinout and program memory size are for reference only and are not visible in the final commercial product order code. - `xxx' represents the code name defined by STMicroelectronics: It denotes the ROM code, pinout and program memory size. - R = Tape and Reel (left blank if Tray)
Figure 103. FASTROM commercial product code structure
DEVICE PACKAGE TEMP RANGE xxx R E
E = Lead-free (ECOPACK(R)) Conditioning options: R = Tape and Reel (left blank if Tray) Code name (defined by STMicroelectronics) (denotes ROM code, pinout and program memory size) A = -40 to 85C B = -40 to 105C C = -40 to 125C T = Low profile quad flat pack ST72P321B
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Device configuration and ordering information Table 147. ROM factory coded device types
Order code(1) ST72321B(J6)TA/xxxRE ST72321B(J7)TA/xxxRE ST72321B(J9)TA/xxxRE ST72321B(AR6)TA/xxxRE ST72321B(AR7)TA/xxxRE ST72321B(AR9)TA/xxxRE ST72321B(R6)TA/xxxRE ST72321B(R7)TA/xxxRE ST72321B(R9)TA/xxxRE ST72321B(J6)TB/xxxRE ST72321B(J7)TB/xxxRE ST72321B(J9)TB/xxxRE ST72321B(AR6)TB/xxxRE ST72321B(AR7)TB/xxxRE ST72321B(AR9)TB/xxxRE ST72321B(R6)TB/xxxRE ST72321B(R7)TB/xxxRE ST72321B(R9)TB/xxxRE ST72321B(J6)TC/xxxRE ST72321B(J7)TC/xxxRE ST72321B(J9)TC/xxxRE ST72321B(AR6)TC/xxxRE ST72321B(AR7)TC/xxxRE ST72321B(AR9)TC/xxxRE ST72321B(R6)TC/xxxRE ST72321B(R7)TC/xxxRE ST72321B(R9)TC/xxxRE LQFP64 (14 x 14) LQFP64 (10 x 10) LQFP44 (10 x 10) LQFP64 (14 x 14) LQFP64 (10 x 10) LQFP44 (10 x 10) LQFP64 (14 x 14) LQFP64 (10 x 10) LQFP44 (10 x 10) Package Memory (Kbytes) 32 48 60 32 48 60 32 48 60 32 48 60 32 48 60 32 48 60 32 48 60 32 48 60 32 48 60
ST72321Bxxx-Auto
Temperature range
-40C to +85C
-40C to +105C
-40C to +125C
1. - The two or three characters in parentheses which represent the pinout and program memory size are for reference only and are not visible in the final commercial product order code. - `xxx' represents the code name defined by STMicroelectronics: It denotes the ROM code, pinout and program memory size. - R = Tape and Reel (left blank if Tray)
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Device configuration and ordering information
Figure 104. ROM commercial product code structure
DEVICE PACKAGE TEMP RANGE / xxx R E
E = Lead-free (ECOPACK(R)) Conditioning options: R = Tape and Reel (left blank if Tray) Code name (defined by STMicroelectronics) (denotes ROM code, pinout and program memory size) A = -40 to 85C B = -40 to 105C C = -40 to 125C T = Low profile quad flat pack ST72321B
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Device configuration and ordering information
ST72321Bxxx-Auto
ST72321B-Auto MIcrocontroller FASTROM/ROM Option List (Last update: October 2007) Customer: Address: Contact: Phone No: Reference: ................................... ................................... ................................... ................................... ................................... ...................................
The FASTROM/ROM code name is assigned by STMicroelectronics. FASTROM/ROM code must be sent in .S19 format. .Hex extension cannot be processed. Device Type/Memory Size/Package (check only one option): -----------------------------------------------------------------------------------------------------------------------------------------------------FASTROM DEVICE: 60K 48K 32K -----------------------------------------------------------------------------------------------------------------------------------------------------LQFP44 10x10: [ ] ST72P321B(J9)T [ ] ST72P321B(J7)T [ ] ST72P321B(J6)T LQFP64 10x10: [ ] ST72P321B(AR9)T [ ] ST72P321B(AR7)T [ ] ST72P321B(AR6)T LQFP64 14x14: [ ] ST72P321B(R9)T [ ] ST72P321B(R7)T [ ] ST72P321B(R6)T ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ROM DEVICE: 60K 48K 32K ------------------------------------------------------------------------------------------------------------------------------------------------------LQFP44 10x10: [ ] ST72321B(J9)T [ ] ST72321B(J7)T [ ] ST72321B(J6)T LQFP64 10x10: [ ] ST72321B(AR9)T [ ] ST72321B(AR7)T [ ] ST72321B(AR6)T LQFP64 14x14: [ ] ST72321B(R9)T [ ] ST72321B(R7)T [ ] ST72321B(R6)T ------------------------------------------------------------------------------------------------------------------------------------------------------Conditioning for LQFP package (check only one option): [ ] Tape & Reel Temperature range : [ ] A (-40C to +85C) [ ] B (-40C to +105C) [ ] C (-40C to +125C) [ ] No [ ] Yes "_ _ _ _ _ _ _ _ _ _ " (10 characters max) Authorized characters are letters, digits, '.', '-', '/' and spaces only. [ ] Tray
Special Marking:
Clock Source Selection:
[ ] Resonator: [ ] LP: Low power resonator (1 to 2 MHz) [ ] MP: Medium power resonator (2 to 4 MHz) [ ] MS: Medium speed resonator (4 to 8 MHz) [ ] HS: High speed resonator (8 to 16 MHz) [ ] Internal RC [ ] External Clock (sets MP Medium Power resonator in Option Byte) [ ] Disabled [ ] Disabled [ ] Med.threshold [ ] 256 Cycles [ ] Enabled [ ] High threshold [ ] Low threshold [ ] 4096 Cycles
PLL (1)(2) LVD Reset
Reset Delay Watchdog Selection Halt when Watchdog on Readout Protection Date
[ ] Software Activation [ ] Hardware Activation [ ] Reset [ ] Disabled [ ] No reset [ ] Enabled
. . . . . . . . Signature . . . . . . . . . . . . . . . .
Note 1 : PLL must be disabled if internal RC Network is selected. Note 2 : The PLL can be enabled only if the resonator is configured to "Medium Power: 2~4 MHz". CAUTION: The Readout Protection binary value is inverted between ROM and Flash products. The option byte checksum will differ between ROM and Flash. Please download the latest version of this option list from www.st.com.
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Device configuration and ordering information
21.3
21.3.1
Development tools
Introduction
Development tools for the ST7 microcontrollers include a complete range of hardware systems and software tools from STMicroelectronics and third-party tool suppliers. The range of tools includes solutions to help you evaluate microcontroller peripherals, develop and debug your application, and program your microcontrollers.
21.3.2
Evaluation tools and starter kits
ST offers complete, affordable starter kits and full-featured evaluation boards that allow you to evaluate microcontroller features and quickly start developing ST7 applications. Starter kits are complete, affordable hardware/software tool packages that include features and samples to help you quickly start developing your application. ST evaluation boards are open-design, embedded systems, which are developed and documented to serve as references for your application design. They include sample application software to help you demonstrate, learn about and implement your ST7's features.
21.3.3
Development and debugging tools
Application development for ST7 is supported by fully optimizing C Compilers and the ST7 Assembler-Linker toolchain, which are all seamlessly integrated in the ST7 integrated development environments in order to facilitate the debugging and fine-tuning of your application. The Cosmic C Compiler is available in a free version that outputs up to 16 Kbytes of code. The range of hardware tools includes cost effective ST7-DVP3 series emulators. These tools are supported by the ST7 Toolset from STMicroelectronics, which includes the STVD7 integrated development environment (IDE) with high-level language debugger, editor, project manager and integrated programming interface.
21.3.4
Programming tools
During the development cycle, the ST7-DVP3 and ST7-EMU3 series emulators and the RLink provide in-circuit programming capability for programming the Flash microcontroller on your application board. ST also provides a low-cost dedicated in-circuit programmer, the ST7-STICK, as well as ST7 socket boards which provide all the sockets required for programming any of the devices in a specific ST7 subfamily on a platform that can be used with any tool with incircuit programming capability for ST7. For production programming of ST7 devices, ST's third-party tool partners also provide a complete range of gang and automated programming solutions, which are ready to integrate into your production environment. For additional ordering codes for spare parts, accessories and tools available for the ST7 (including from third party manufacturers), refer to the online product selector at www.st.com/mcu.
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Device configuration and ordering information Table 148. STMicroelectronics development tools
Emulation Supported products ST7 DVP3 series Emulator ST72321BAR, ST72F321BAR ST72321BR, ST72F321BR ST72321BJ, ST72F321BJ ST7MDT20DVP3 Connection kit ST7MDT20T6A/DVP ST7MDT20T64/DVP ST7MDT20T44/DVP ST7 EMU3 series Emulator
ST72321Bxxx-Auto
Programming
Active probe and T.E.B.
ICC socket board
ST7MDT20MEMU3
ST7MDT20MTEB
ST7SB20M/xx(1)
ST7MDT20JEMU3
ST7MDT20JTEB
ST7SB20J/xx(1)
1. Add suffix /EU, /UK, /US for the power supply of your region.
Table 149. Suggested list of socket types
Device LQFP64 14 x14 LQFP64 10 x10 LQFP44 10 x10 Socket (supplied with ST7MDT20M-EMU3) CAB 3303262 YAMAICHI IC149-064-*75-*5 YAMAICHI IC149-044-*52-*5 Emulator adapter (supplied with ST7MDT20M-EMU3) CAB 3303351 YAMAICHI ICP-064-6 YAMAICHI ICP-044-5
21.3.5
Socket and emulator adapter information
For information on the type of socket that is supplied with the emulator, refer to the suggested list of sockets in Table 149.
Note:
Before designing the board layout, it is recommended to check the overall dimensions of the socket as they may be greater than the dimensions of the device. For footprint and other mechanical information about these sockets and adapters, refer to the manufacturer's datasheet.
Related documentation
ST7 Visual Develop Software Key Debugging Features (AN 978) ST7 Visual Develop for ST7 Cosmic C toolset users (AN 1938) ST7 Visual Develop for ST7 Assembler Linker toolset users (AN 1940)
21.4
ST7 application notes
All relevant ST7 application notes can be found on www.st.com.
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ST72321Bxxx-Auto
Known limitations
22
22.1
22.1.1
Known limitations
All Flash and ROM devices
Unexpected reset fetch
If an interrupt request occurs while a "POP CC" instruction is executed, the interrupt controller does not recognize the source of the interrupt and, by default, passes the RESET vector address to the CPU.
Workaround
To solve this issue, a "POP CC" instruction must always be preceded by a "SIM" instruction.
22.1.2
External interrupt missed
To avoid any risk of generating a parasitic interrupt, the edge detector is automatically disabled for one clock cycle during an access to either DDR and OR. Any input signal edge during this period will not be detected and will not generate an interrupt. This case can typically occur if the application refreshes the port configuration registers at intervals during runtime.
Workaround
The workaround is based on software checking the level on the interrupt pin before and after writing to the PxOR or PxDDR registers. If there is a level change (depending on the sensitivity programmed for this pin) the interrupt routine is invoked using the call instruction with three extra PUSH instructions before executing the interrupt routine (this is to make the call compatible with the IRET instruction at the end of the interrupt service routine). But detection of the level change does not make sure that edge occurs during the critical 1 cycle duration and the interrupt has been missed. This may lead to occurrence of same interrupt twice (one hardware and another with software call). To avoid this, a semaphore is set to `1' before checking the level change. The semaphore is changed to level '0' inside the interrupt routine. When a level change is detected, the semaphore status is checked. If it is `1', it means that the last interrupt has been missed. In this case, the interrupt routine is invoked with the call instruction. There is another possible case, that is, if PxOR or PxDDR are written to with global interrupts disabled (interrupt mask bit set). In this case, the semaphore is changed to `1' when the level change is detected. Detecting a missed interrupt is done after the global interrupts are enabled (interrupt mask bit reset) and by checking the status of the semaphore. If it is `1', it means that the last interrupt was missed and the interrupt routine is invoked with the call instruction. To implement the workaround, the following software sequence is to be followed for writing into the PxOR/PxDDR registers. The example is for Port PF1 with falling edge interrupt sensitivity. The software sequence is given for both cases (global interrupts disabled / global interrupts enabled): Case 1: Writing to PxOR or PxDDR with global interrupts enabled: LD A,#01
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LD sema,A ; set the semaphore to '1' LD A,PFDR AND A,#02 LD X,A ; store the level before writing to PxOR/PxDDR LD A,#$90 LD PFDDR,A ; Write to PFDDR LD A,#$ff LD PFOR,A ; Write to PFOR LD A,PFDR AND A,#02 LD Y,A ; store the level after writing to PxOR/PxDDR LD A,X ; check for falling edge cp A,#02 jrne OUT TNZ Y jrne OUT LD A,sema ; check the semaphore status if edge is detected CP A,#01 jrne OUT call call_routine ; call the interrupt routine OUT:LD A,#00 LD sema,A .call_routine ; entry to call_routine PUSH A PUSH X PUSH CC
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Known limitations
.ext1_rt ; entry to interrupt routine LD A,#00 LD sema,A IRET Case 2: Writing to PxOR or PxDDR with global interrupts disabled: SIM ; set the interrupt mask LD A,PFDR AND A,#$02 LD X,A ; store the level before writing to PxOR/PxDDR LD A,#$90 LD PFDDR,A ; Write into PFDDR LD A,#$ff LD PFOR,A ; Write to PFOR LD A,PFDR AND A,#$02 LD Y,A ; store the level after writing to PxOR/PxDDR LD A,X ; check for falling edge cp A,#$02 jrne OUT TNZ Y jrne OUT LD A,#$01 LD sema,A ; set the semaphore to '1' if edge is detected RIM ; reset the interrupt mask LD A,sema ; check the semaphore status CP A,#$01
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jrne OUT call call_routine ; call the interrupt routine RIM OUT: RIM JP while_loop .call_routine ; entry to call_routine PUSH A PUSH X PUSH CC .ext1_rt ; entry to interrupt routine LD A,#$00 LD sema,A IRET
22.1.3
Clearing active interrupts outside interrupt routine
When an active interrupt request occurs at the same time as the related flag is being cleared, an unwanted reset may occur.
Note:
Clearing the related interrupt mask will not generate an unwanted reset. Concurrent interrupt context The symptom does not occur when the interrupts are handled normally, that is, when:

The interrupt flag is cleared within its own interrupt routine The interrupt flag is cleared within any interrupt routine The interrupt flag is cleared in any part of the code while this interrupt is disabled
If these conditions are not met, the symptom can be avoided by implementing the following sequence: Perform SIM and RIM operation before and after resetting an active interrupt request. Example: SIM Reset interrupt flag RIM Nested interrupt context
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Known limitations
The symptom does not occur when the interrupts are handled normally, that is, when:

The interrupt flag is cleared within its own interrupt routine The interrupt flag is cleared within any interrupt routine with higher or identical priority level The interrupt flag is cleared in any part of the code while this interrupt is disabled
If these conditions are not met, the symptom can be avoided by implementing the following sequence: PUSH CC SIM Reset interrupt flag POP CC
22.1.4
SCI wrong break duration
Description
A single break character is sent by setting and resetting the SBK bit in the SCICR2 register. In some cases, the break character may have a longer duration than expected:

20 bits instead of 10 bits if M = 0 22 bits instead of 11 bits if M = 1
In the same way, as long as the SBK bit is set, break characters are sent to the TDO pin. This may lead to generating one break more than expected.
Occurrence
The occurrence of the problem is random and proportional to the baud rate. With a transmit frequency of 19200 baud (fCPU = 8 MHz and SCIBRR = 0xC9), the wrong break duration occurrence is around 1%.
Workaround
If this wrong duration is not compliant with the communication protocol in the application, software can request that an Idle line be generated before the break character. In this case, the break duration is always correct assuming the application is not doing anything between the idle and the break. This can be ensured by temporarily disabling interrupts. The exact sequence is:

Disable interrupts Reset and Set TE (IDLE request) Set and Reset SBK (Break Request) Re-enable interrupts
22.1.5
16-bit timer PWM mode
In PWM mode, the first PWM pulse is missed after writing the value FFFCh in the OC1R register (OC1HR, OC1LR). It leads to either full or no PWM during a period, depending on the OLVL1 and OLVL2 settings.
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Known limitations
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22.1.6
TIMD set simultaneously with OC interrupt
If the 16-bit timer is disabled at the same time the output compare event occurs, the output compare flag then gets locked and cannot be cleared before the timer is enabled again.
Impact on the application
If the output compare interrupt is enabled, then the output compare flag cannot be cleared in the timer interrupt routine. Consequently, the interrupt service routine is called repeatedly.
Workaround
Disable the timer interrupt before disabling the timer. Again while enabling, first enable the timer, then the timer interrupts.
Perform the following to disable the timer: - - TACR1 or TBCR1 = 0x00h; // Disable the compare interrupt TACSR | or TBCSR | = 0x40; // Disable the timer TACSR & or TBCSR & = ~0x40; // Enable the timer TACR1 or TBCR1 = 0x40; // Enable the compare interrupt
Perform the following to enable the timer again: - -
22.1.7
I2C multimaster
In multimaster configurations, if the ST7 I2C receives a START condition from another I2C master after the START bit is set in the I2CCR register and before the START condition is generated by the ST7 I2C, it may ignore the START condition from the other I2C master. In this case, the ST7 master will receive a NACK from the other device. On reception of the NACK, ST7 can send a restart and Slave address to re-initiate communication.
22.1.8
Pull-up always active on PE2
The I/O port internal pull-up is always active on I/O port E2. As a result, if PE2 is in output mode low level, current consumption in Halt/Active Halt mode is increased.
22.2
22.2.1
Limitations specific to 44-pin 32 Kbyte ROM devices
Halt/Active Halt mode power consumption with external clock enabled
The power consumption in Halt/Active Halt mode with external clock enabled is increased by 40A typ.
22.2.2
Active Halt power consumption
The power consumption in Active Halt mode is 190A typ. and 300A max. These measurements are done with an external clock source. However to obtain the total device consumption, the clock source consumption has to be added.
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Known limitations
22.2.3
IC exit from Halt/Active Halt
Contrary to the behavior specified in the datasheet, the I2C interrupt is capable of exiting the device from Halt/Active Halt mode.
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Revision history
ST72321Bxxx-Auto
23
Revision history
Table 150. Document revision history
Date 05-Oct-2007 Revision 1 Initial release Changes
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